72
IBM Power 595 Technical Overview and Introduction
Several methods for activating CoD POWER6 processors are available. Table 2-13 lists the
CoD processor activation features and corresponding CoD modes. Additional information
about the CoD modes are provided in section 3.3, “Capacity on Demand” on page 111.
Table 2-13 CoD processor activation features
Each 8-core book contains four dual-threaded 64-bit SMP POWER6 processors chips
packaged in four MCMs as shown in Figure 2-29 on page 73. The processor book also
provides 32 DIMM slots for DDR2 memory DIMMs and four GX bus slots for remote I/O hubs
cards (RIO-2 and 12x) that are used to connect system I/O drawers.
#4695
0/8-core POWER6 5.0 GHz CoD 0-core Active Processor Book
Note:
The minimum configuration requirement is one 4.2 GHz processor book with three
processor activations, or two 5.0 GHz processor books with six processor activations.
Feature
code
Description
CoD Mode
Support
AIX
IBM i
Li
n
u
x
#4754
Processor activation for processor book #4694
Permanent
9
9
9
#4755
Processor activation for processor book #4695
Permanent
9
9
9
#7971
On/Off Processor Enablement
On/Off, Utility
9
9
9
#7234
On/Off Processor CoD Billing, 1 Proc-Day, for #4694
On/Off
9
–
9
#7244
On/Off Processor CoD Billing, 1 Proc-Day, for #4695
On/Off
9
–
9
#5945
On/Off Processor CoD Billing, 1 Proc-Day, for #4694,
IBM i
On/Off
–
9
–
#5946
On/Off Processor CoD Billing, 1 Proc-Day, for #4695,
IBM i
On/Off
–
9
–
#5941
100 Processor Minutes for #4694
Utility
9
–
9
#5942
100 Processor Minutes for #4695
Utility
9
–
9
#5943
100 Processor Minutes for #4694, IBM i
Utility
–
9
–
#5944
100 Processor Minutes for #4694, IBM i
Utility
–
9
–
Feature code
Description
Summary of Contents for Power 595
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