62
IBM Power 750 and 760 Technical Overview and Introduction
2.4.3 Software licensing and CoD
For software licensing considerations with the various CoD offerings, see the most recent
revision of the Power Systems Capacity on Demand User’s Guide:
http://www.ibm.com/systems/power/hardware/cod
2.5 System bus
This section provides additional information related to the internal buses.
2.5.1 I/O buses and GX++ card
Each Power 750 Express server (8408-E8D) and each Power 760 server (9109-RMD)
supports up to four processor dual chip modules (DCMs). For the Power 750
Express server, each of the four processor DCMs is an 8-core DCM packaged with two 4-core
chips. All 8-core processor DCMs are either 3.5 or 4.0 GHz mounted on a dedicated card with
a granularity of one DCM. For the Power 760 server, each of the four processor DCMs is a
0/12-core CUoD DCM packaged with two 6-core chips. All 0/12-core CUoD processor DCMs
are either 3.1 GHz or 3.4 GHz mounted on a dedicated card with a granularity of one DCM.
In the Power 750 Express server, each processor DCM is a 64-bit, 8-core
processor packaged on a dedicated card with a maximum of 64 DDR3 DIMMs, 10 MB of L3
cache per core, and 256 KB of L2 cache per core. A Power 750 Express server can be
populated with one, two, three, or four DCMs providing 8, 16, 24, or 32 cores. All the cores are
active.
In the Power 760, each processor DCM is a 64-bit, 0/12-core CUoD processor,
packaged on a dedicated card with a maximum of 64 DDR3 DIMMs, 10 MB of L3 cache per
core, and 256 KB of L2 cache per core. A Power 760 server can be populated with one, two,
three, or four DCMs providing 12, 24, 36, or 48 cores. A fully populated Power 760 server with
four DCMs has a minimum of eight cores activated and up to a maximum of 48 cores with a
CUoD granularity of one core.
Each Power 750 Express or Power 760 server provides a total of four GX++ buses available
for I/O connectivity and expansion. Two 4-byte GX++ buses off the DCM0 socket are routed
through the midplane to the I/O backplane and drive two P7IOC chips. The two remaining
GX++ buses are routed off of DCM1 socket to the Midplane and feed GX++ adapter slots.
Therefore, a minimum of two processor cards must be installed to enable two GX++ adapter
slots. These GX++ adapter slots are not hot-pluggable and do not share space with any of the
PCIe slots. Table 2-10 on page 63 shows the I/O bandwidth for available processors cards.
The frequency for these buses are asynchronous to the CPU core clock and therefore will
always be constant regardless of CPU core frequency.
