DIMM installation sequence:
Depending on the server model, the server may come with a minimum of one 2
GB or 4 GB DIMM installed in slot 1. When you install additional DIMMs, install
them in the order shown in the following table to optimize system performance.
In general, all three channels on the memory interface for each microprocessor can
be populated in any order and have no matching requirements.
Table 21. Normal mode DIMM installation sequence
Number of installed
microprocessor
DIMM connector population sequence
One microprocessor
installed
1, 4, 9, 12, 2, 5, 8, 11, 3, 6, 7, 10
Two microprocessors
installed
1, 13, 4, 16, 9, 21, 12, 24, 2, 14, 5, 17, 8, 20, 11, 23, 3, 15, 6, 18,
7, 19, 10, 22
Memory mirrored channel:
Memory mirrored channel mode replicates and stores data on two pairs of DIMMs
within two channels simultaneously.
If a failure occurs, the memory controller switches from the primary pair of
memory DIMMs to the backup pair of DIMMs. To enable memory mirrored
channel through the Setup utility, select
System Settings
>
Memory
. For more
information, see “Using the Setup utility” on page 106. When you use the memory
mirrored channel feature, consider the following information:
v
When you use memory mirrored channel, you must install a pair of DIMMs at a
time. The two DIMMs in each pair must be identical in size, type, and rank
(single, dual, or quad), and organization, but not in speed. The channels run at
the speed of the slowest DIMM in any of the channels.
v
The maximum available memory is reduced to half of the installed memory
when memory mirrored channel is enabled. For example, if you install 64 GB of
memory using RDIMMs, only 32 GB of addressable memory is available when
you use memory mirrored channel.
v
For UDIMMs, DIMM connectors 3, 6, 7, and 10 for microprocessor 1 and DIMM
connectors 15, 18, 19, and 22 for microprocessor 2 are not used in memory
mirrored channel mode.
The following diagram lists the DIMM connectors on each memory channel.
The following table shows the installation sequence for memory mirrored channel
mode:
Figure 138. Connectors on each memory channel
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