Chapter 2. Architecture and technical overview
33
Table 2-3 Theoretical throughput rates
2.4 I/O buses
This section provide additional information that is related to the internal RIO-2 buses and GX+
buses.
The QCM or DCM provides a GX+ bus. In the past, the 6XX bus was the front end from the
processor to memory, PCI Host bridge, cache, and other devices. The follow-on to the 6XX
bus is the GX bus, connecting the processor to the I/O subsystems. Compared with the 6XX
bus, the GX+ bus is both wider and faster and connects to the Enhanced I/O Controller.
The Enhanced I/O Controller is a GX+ to PCI and PCI-X 2.0 Host bridge chip. It contains a
GX+ passthru port and four PCI-X 2.0 buses. The GX+ passthru port allows other GX+ bus
hubs to be connected into the system. Each Enhanced I/O Controller can provide four
separate PCI-X 2.0 buses. Each PCI-X 2.0 bus is 64 bits in width and individually capable of
running either PCI, PCI-X, or PCI-X 2.0 (DDR only).
The p5-520 and p5-520Q systems do not have RIO-2 ports integrated on the system planar
to connect supported external I/O subsystems. As shown in Figure 2-9 on page 34, one
Remote I/O expansion card (FC 2888) is required to connect the supported external I/O
subsystems. When this card is present, the Enhanced I/O Controller routes the GX+ bus to
the external RIO-2 ports.
Processor speed
(GHz)
Processor Type
Cores
Memory
(GBps)
L2 to L3
(GBps)
GX+
(GBps)
1.65
1-core
21.1
26.4
4.4
1.65
2-core
21.1
26.4
4.4
1.9
2-core
21.1
30.4
5.1
2.1
1-core
21.1
33.6
5.6
2.1
2-core
21.1
33.6
5.6
1.5
4-core
21.1
48
4
1.65
4-core
21.1
52.8
4.4
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