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RS/6000 SP and Clustered IBM
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pSeries Systems Handbook
2.2.1 375 MHz POWER3 processor
The 375 MHz POWER3 design contains a superscalar core, which is comprised
of eight execution units, supported by a high bandwidth memory interface
capable of performing four floating-point operations per clock cycle. The 375
MHz POWER3 design allows concurrent operation of fixed-point, load/store,
branch, and floating-point instructions. There is a 32 KB instruction and 64 KB
data level 1 cache integrated within a single chip in .22 um CMOS technology.
Both instruction and data caches are parity protected.
The level 2 cache controller is integrated into the 375 MHz POWER3-II
microprocessor with the data arrays and directory being implemented with
external SRAM modules. The 375 MHz POWER3 microprocessor has a
dedicated external interface (separate from 6xx bus interface) for the level 2
cache accesses. Access to the 6xx bus and the level 2 cache can occur
simultaneously. The level 2 cache is a unified cache (that is, it holds both
instruction and data), and is configured for four-way set associative configuration.
The external interface to the 8 MB of level 2 cache has 256-bit width and
operates at 250 MHz. This interface is ECC protected.
The 375 MHz POWER3 microprocessor is designed to provide high performance
floating-point computation. There are two floating-point execution units, each
supporting 3-cycle latency, 1-cycle throughput, and double/single precision
Multiply-Add execution rate. Hence, the 375 MHz POWER3 microprocessor is
capable of executing four floating-point operations per clock cycle, which results
in a peak throughput of 1500 MFLOPS.
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