and read operations. If memory data is written to a location in the
cache and the cache line is in the “modified” state, the corresponding
cache line is written back to system memory and invalidated.
When the microprocessor performs a memory read, the data address
is used to find the data in the cache. If the data is found (a hit), it is
read from the cache memory and no external bus cycle occurs. If
the data is not found (a miss), an external bus cycle is used to read
the data from system memory. If the address of the missed data is
in cacheable address space, the data is stored in the cache memory
and the remainder of the cache line is read.
When the microprocessor performs a memory write, the data
address is used to search the cache. If the address is found (hit),
the data is written to the cache and no external bus cycle is used to
write the data to system memory. (If the address of the write
operation was not in the cache memory but was in cacheable
address space, the data is read back into the cache memory and the
remainder of the cache line is read.)
Cacheable Address Space
Cacheable address space is defined as system memory that resides
on the system board (0–640 KB and 1 MB–256 MB). Cacheability of
system memory is up to 64 MB in the L2 cache. Nothing in address
range hex A0000–BFFFF, I/O address space, or memory in any AT
slot is cached.
ROM address space (hex C0000–C9FFF and F0000–FFFFF) is L1
cacheable for
code read operations only. If data in this address
range is already in cache memory and the address range is written
to, the cached line is invalidated and is read again from RAM, where
the BIOS is shadowed.
Bus Adapter
When the computer is attached to the ThinkPad SelectaDock III
docking system, the PCI adapters or AT-bus adapters can be used
through the docking system.
System Board
2-3
Summary of Contents for ThinkPad 770
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