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3-3 FREQUENCY SYNTHESIZER CIRCUITS
PLL UNIT
PLL UNIT provides LO signals; 1st LO for TX/RX IF circuits,
2nd RX LO (64.491 MHz), 2nd TX LO (64 MHz), 3rd TX LO
(491 kHz), marker frequency (100 kHz), reference frequency
for the SCOPE UNIT (40 MHz) and clock signal for the DSP
UNIT (12.888 MHz). These LO signals are generated by the
reference signal from the OSC UNIT as reference.
This transeiver employs the Direct Digital Synthesizer (DDS)
which digitally creates arbitrary waveforms and frequencies
from a fixed source frequency, to provide extremely high
resolution and stability frequency and pure waveform.
• Reference frequency signal
The 10 MHz reference frequency signal generated on
the OSC UNIT is applied to the 4th harmonic extractor
(Q702, L702, 703) via buffer (Q30) to produce the 40 MHz
reference signal.
• 1st LO signals
The 40 MHz reference signal from the harmonic extractor
is amplified by Q101, and applied to the DDS (IC101)
as the clock signal. The DDS generates the 10.4122038
–10.4963312 MHz sine waves, and these are passed
through the ceramic filter (FI101; Fc=10.7 MHz) to adjust
the waveform, then applied to the PLL IC (IC201) via buffer
(Q151).
The PLL IC (IC201) controls the oscillating frequency
of 6 VCOs (VCO1 to VCO6) using the reference signal
generated by the DDS as reference frequency.
The output signals of each VCOs (1st LO signals) are
buffer-amplified by Q301, passed through the HPF and
LPF, then amplified by the 1st LO AMPs (Q302 and Q351).
The amplified 1st LO signals are buffer-amplified by Q352,
passed through the LPF, HPF and ATT, then output to the
RF UNIT as 1st LO signals (64.485–124.455 MHz).
• 2nd LO signals
The 40 MHz reference signal from the harmonic extractor is
amplified by IC503, and applied to the DDS (IC501) as the
clock signal. The DDS generates the reference frequency
which controls the oscillating frequency of 64 MHz VCO
(Q541).
The output signal of 64 MHz VCO (Q541) is buffer-amplified
by Q561, and applied to the hybrid divider.
The hybrid divider divides the VCO output into two; 2nd TX
LO and 2nd RX LO.
<2nd TX LO signal>
The VCO output signal from the hybrid divider is passed
through the ATT, and applied to the 2nd LO AMP (Q591).
The amplified VCO output signal is passed through the BPF,
then entered to the RF UNIT as the 2nd TX LO signal.
<2nd RX LO signal>
The VCO output signal from the hybrid divider is passed
through the ATT, and applied to the 2nd LO AMP (Q801).
The amplified VCO output signal is passed through the ATT
and, applied to the 2nd LO mixer (D821) and mixed with
the 491 kHz 3rd TX LO signal from the 3rd TX LO oscillator
(IC651), to convert into the 64.491 MHz 2nd RX LO signal.
The converted 2nd RX LO signal is passed through the
ATT and BPF, and applied to the 2nd LO AMP (Q831). The
amplified signal is entered to the RF UNIT as the 2nd RX
LO signal.
• 3rd TX LO signal
The 40 MHz reference signal from the harmonic extractor
is amplified by IC652, and applied to the DDS (IC565) as
the clock signal. Using the clock signal, the DDS directly
generates the 491 kHz 3rd TX LO signal.
The output signal of DDS is passed through the LPF and
HPF, and applied to the buffer AMP (Q680). The buffer-
amplified 2rd TX LO signal is entered to the RF UNIT via
ATT.
• DSP system clock
The 40 MHz reference signal from the harmonic extractor
is amplified by IC1651, and applied to the DDS (IC1652)
as the clock signal. Using the clock signal, the DDS directly
generates 12.288 MHz system clock signal. The system
clock signal is passed through the LPF and HPF, and
applied to the buffer (Q1680). The buffer-amplified system
clock signal is entered to the MAIN UNIT via ATT.
• Scope clock
The 40 MHz reference signal from the harmonic extractor is
amplified by Q1601, and entered to the SCOPE UNIT.
VCO
Oscillator
component
Oscillating frequency
VCO1
Q220
64.485–72.454999 MHz
VCO2
Q230
72.455–79.454999 MHz
VCO3
Q240
79.455–86.454999 MHz
VCO4
Q250
86.455–94.454999 MHz
VCO5
Q260
94.455–109.454999 MHz
VCO6
Q270
109.455–124.455 MHz
