3 - 4
3-3 PLL CIRCUIT
3-3-1 GENERAL (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains of the TX-VCO and RX-VCO cir-
cuits. The oscillated signals are applied to the buffer ampli-
fiers (Q43, Q12) then applied to the PLL IC (IC2, pin 8). IC2
is a dual PLL IC which controls VCO circuits for TX and RX.
The PLL circuit, using a one chip PLL IC (IC2), directly gen-
erates the transmit frequency and receive 1st IF frequency
with VCOs. The PLL sets the divided ratio based on serial
data from the CPU on the FRONT unit and compares the
phases of VCO signals with the reference oscillator fre-
quency. The PLL IC detects the out-of-step phase and out-
put from pin 9 for TX and RX, respectively. The reference
frequency (12.8 MHz) is oscillated at X1.
3-3-2 TX LOOP
The generated signal at the TX-VCO (Q44, D64) enters the
PLL IC (IC2, pin 8), and is divided at the programmable
divider section and is then applied to the phase detector
section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 9.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R61, R62, C59, C60), and then
applied to the varactor diode (D64) of the TX-VCO to stabi-
lize the oscillated frequency.
3-3-3 RX LOOP
The generated signal at the RX-VCO (Q59, D65) enters the
PLL IC (IC2, pin 8), and is divided at the programmable
divider section. The divided signal is then applied to the
phase detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 9.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R61, R62, C59, C60), and then
applied to the varactor diode (D65) of the RX-VCO to stabi-
lize the oscillated frequency. The lock voltage is also used
for the receiver circuit for the bandpass filter center frequen-
cy. The lock voltage from the PLL IC (IC2, pin 9) passes
through the low-pass filter, and is applied to the tune buffer
amplifier (Q79). The amplified signal is applied to the RF
bandpass filters (D7, D8 and D6, D37) via the tune adjust-
ment pot (R59).
3-3-4 VCO CIRCUIT
The VCO outputs from Q44 (TX) and Q59 (RX) are buffer
amplified at Q43, and are applied to the buffer amplifiers
(Q14, Q15). The amplified signal is applied to the T/R switch
(D10, D11). The receive LO signal is applied to the 1st mixer
circuit (Q2), and the transmit signal is applied to the pre-
amplifier (Q42).
A portion of the VCO signal is amplified at the buffer ampli-
fier (Q12), and then fed back to the PLL IC (IC2, pin 8).
• PLL circuit
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
TCXO (X1)
12.8 MHz
Q44,
D64
TX VCO
RX VCO
Buff.
D10
D11
Q12
Q43
3
4
5
SCK
IC2 (PLL IC)
SO
PLSTB
to transmitter circuit
to 1st mixer circuit (Q2)
14
9
LPF
8
Q59,
D65
Buff.
Q14
Buff.
Q15
TX/RX
switch
Buff.
3
Q83, Q84
to the RF BPF
(D7 and D8, D6 and D37)
38.4 MHz 2nd LO signal
to the 2nd IF IC (IC40, pin 2)
Tune
buff.
R59
(RF BPF adjustment)
Q79
