5
7.1 Introduction ................................................................................... 42
Appendix A. Watch-Dog Timer ................................................... 43
Appendix B. I/O Address Map..................................................... 48
B.1 System I/O Address Map ............................................................... 48
B.2 DMA channel assignments............................................................. 49
B.3 Interrupt assignments .................................................................... 49
B.4 1
st
MB memory map ...................................................................... 50