Advanced Chipset Setup Menu 4-19
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Advanced Chipset Setup Menu
This setup is very important to maintain system stability. The optimal default
setting is recommended.
Configure SDRAM Timing by SPD
This option provides DIMM Plug-n-Play support by the Serial Presence Detect
(SPD) mechanism via the System Management Bus (SMBus) interface. You can
disable this option to manage the following four SDRAM timing options by
yourself. In addition, SDRAM operating timings may follow serial presence from
the EEPROM content by setting this option to
Enabled
, and all of SDRAM timing
options will be not available and hidden.
SDRAM RAS# to CAS# Delay
This option controls the number of SDRAM Clocks (SCLKs) from a row activate
command to a read or write command. Normally, the option will be set to
3 SCLKs
.
SDRAM RAS# Precharge
This option controls the number of SCLKs for RAS# precharge.
SDRAM CAS# Latency
This option controls the number of SCLKs between the time a read command is
sampled by the SDRAMs and the time the North Bridge, 82443BX, samples
correspondent data from the SDRAMs. For a registered DIMM with CAS#
Latency = 2, this option should be set to
2 SCLKs
to acquire better memory
performance.
SDRAM Leadoff Cmd Timing
This option is used to control when the SDRAM command pins (SRASx#, SCASx#
and Wex#) and CSx# are considered valid on leadoffs for CPU cycles. If you select
Auto
, this timing will be automatically initialized and set by the BIOS.
