ISA BUS SIGNAL DESCRIPTIONS
The following is a description of the ISA Bus signals. All signal
lines are TTL-compatible.
AEN (O)
Address Enable (AEN) is used to degate the microprocessor and other devices
from the I/O channel to allow DMA transfers to take place. When this line is
active, the DMA controller has control of the address bus, the data-bus Read
command lines (memory and I/O), and the Write command lines (memory and
I/O).
BALE (O) (Buffered)
Address Latch Enable (BALE) is provided by the bus controller and is used on
the system board to latch valid addresses and memory decodes from the
microprocessor. It is available to the I/O channel as an indicator of a valid
microprocessor or DMA address (when used with AEN). Microprocessor
addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced
high during DMA cycles.
BCLK (O)
BCLK is the system clock. The clock has a 50% duty cycle. This signal should
only be used for synchronization. It is not intended for uses requiring a fixed
frequency.
CHRDY (I)
I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O
device to lengthen I/O or memory cycles. Any slow device using this line
should drive it low immediately upon detecting its valid address and a Read or
Write command. Machine cycles are extended by an integral number of clock
cycles. This signal should be held low for no more than 2.5 microseconds.
D[15::0] (I/O)
Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor,
memory, and I/O devices. D15 is the most-significant bit and D0 is the
least-significant bit. All 8-bit devices on the I/O channel should use D[7::0] for
communications to the microprocessor. The 16-bit devices will use D[15::0].
To support 8-bit devices, the data on D[15::8] will be gated to D[7::0] during
8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit
devices will be converted to two 8-bit transfers.
DAK[7::5]#, DAK[3::0]# (O)
DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA
requests DRQ[7::5] and DRQ[3::0]. They are active low.
ISA REFERENCE
2-4
TECHNICAL REFERENCE
Summary of Contents for SB586TCP/166
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Page 11: ...SPECIFICATIONS TECHNICAL REFERENCE 1 3...
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Page 94: ...This page intentionally left blank ADVANCED SETUP 5 18 TECHNICAL REFERENCE...
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