Manual Number: 40110-005-2
Page 8
Second, the ADRx mode bit must be set to 0, which blocks the clock to the watchdog timer circuit,
thus scheduling a hardware reset in about 1.5 seconds.
Refreshing the watchdog timer consists of the software in the application first toggling the ADRx
bit to 1, thus clearing the watchdog timer delay, and then setting it to 0, which schedules a system
reset in 1.5 seconds.
A set of watchdog timer software code and sample programs are available from Technical
Support.
Power Fail Detection
A hardware reset is issued when on-board voltage drops below 4.75 volts.
Keyboard Interface
The processor board is compatible with an AT type keyboard. The keyboard connection can be
made by using the P5A Combo I/O connector. Keyboard voltage is protected by a self-resetting
fuse.
Battery
A built-in lithium battery is provided, for ten years of data retention for CMOS memory.
Power Requirements
+3.3V @ 700 mAmps typical
+5V @ 6.2 Amps typical
+12V @ < 100 mAmps typical
-12V @ < 100 mAmps typical
Temperature/Environment
Operating Temperature:
0º C. to 60º C.
Storage Temperature:
- 40º C. to 70º C.
Humidity Maximum:
90% non-condensing
Mean Time Between Failures (MTBF)
> 75,000 POH (Power-On Hours)
System Performance (Norton SI 32)
200MHz/512K cache - 2.35
200MHz/256K cache - 2.35
Agency Approvals
FCC Conformity with:
47CFR Part 15, Subpart B
CE Conformity with:
EU EMC Directive 89/336/EEC
EU Low Voltage Directive 72/23/EEC
Summary of Contents for SB686P Series
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