14. Register Descriptions > Register Map
132
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
27
S_TA
Signaled Target Abort
The PEB383 sets this bit to report the signaling of
Target-Abort as target of a transaction on the PCI Interface.
0 = No Target-Abort signaled.
1 = Target-Abort signaled by the PEB383 on its PCI
Interface.
R/W1C
0
26:25
DEVSEL
Device Select Timing
The PEB383 uses medium-speed decoding on its
PCI Interface.
R
01
24
MDP_D
Master Data Parity Error
This bit reports the detection of an uncorrectable data error
by the PEB383.
0 = No uncorrectable data error detected on the PCI
Interface.
1 = Uncorrectable data error detected on the PCI Interface.
R/W1C
0
23
TFBBC
Fast Back-to-Back Capability
0 = Not supported
1 = Supported
This bit is hardwired to 1 when the secondary bus interface
operates in PCI mode, indicating that the bridge can decode
fast back-to-back transactions when the transactions are
from the same master but to different targets.
R
1
22
Reserved
Reserved
R
0
21
DEV66
66-MHz Capable PCI Bus
This bit is hardwired to 1, indicating that the secondary bus
interface can operate at a 66-MHz clock rate.
R
1
20:16
Reserved
Reserved
R
00000
15:12
IO_LA[3:0]
I/O Limit Address
The PEB383 uses this field for I/O address decoding. These
bits define the upper bound of the address range used by
the bridge to forward an I/O transaction from one interface to
the other. These 4 bits correspond to address bits <15:12>.
The address bits <11:0> are assumed equal to 12’hFFF.
R/W
0x0
11:08
ADD_CAP1
Addressing Capability
The PEB383 supports 32-bit I/O addressing.
R
0x1
07:04
IO_BA[3:0]
I/O Base Address
The PEB383 uses this field for I/O address decoding. These
bits define the lower bound of address range used by the
bridge to forward an I/O transaction from one interface to the
other. These 4 bits correspond to address bits <15:12>. The
address bits <11:0> are assumed equal to 12’h0.
R/W
0x0
(Continued)
Bits
Name
Description
Type
Reset value