Index
iv
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
mechanical diagram
memory-mapped I/O addressing
message signaled interrupts (MSI)
message signaled interrupts (MSI-X)
message transactions
message-based interrupts
enhanced message signaled interrupts
message signaled interrupts
N
non-transparent addressing
non-transparent registers
downstream
upstream
O
ordering information
P
PCI capability registers
PCI clocking
PCI errors
PCI Interface
AC timing
PCI reset
PCI transactions
PCIe capability registers
PCIe clocking
PCIe configuration space
PCIe enhanced configuration
PCIe link states
PCIe reset
PCIe transactions
poisoned TLP
power characteristics
power management
power management event
power states
power supply sequencing
prefetchable memory addressing
prefetching algorithm
R
recommended operating conditions
register map
requestor ID
reset
PCI
PCIe
round-robin arbitration
S
SerDes TAP controller
short term caching
system errors
T
TAP controller
target-abort errors
TCK signal
TDI signal
TDO signal
thermal characteristics
timeout errors
timing waveforms
TMS signal
transaction forwarding
PCI to PCIe
PCIe to PCI
transaction management
downstream
upstream
transaction ordering
transactions supported
PCI
PCIe
TRSTn signal
Type 0 configuration transaction
Type 1 configuration transaction
Type 1 to special cycle configuration transaction
Type 1 to Type 0 configuration transaction
Type 1 to Type 1 configuration transaction
typical applications
U
uncorrectable address/attribute errors
uncorrectable data error
Undefined
unsupported request completion status errors
upstream
data path
non-transparent registers
V
VGA addressing
W
warm reset