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PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
3. Data
Path
Topics discussed include the following:
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3.1
Overview
The PEB383 uses two buffering methods for transferring data between its PCIe and PCI ports:
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Two-stage buffering for its upstream data path
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One-stage buffering in its downstream data path
These buffering methods are summarized in the following sub-sections.
3.1.1
Upstream Data Path
Two-stage buffering in the upstream path consists of two different sized buffers for each transaction
type: posted, non-posted, and completion (see
The first-stage buffering in the PCI Core, which supports the store and forward method, meets the
synchronization requirements of PCI and PCIe. This buffer design also provides optimized throughput
and improved latencies.
The second-stage buffering in the PCIe Core, which supports the cut-through method, handles the
possible backpressure due to scaled down link, lack of flow control credits, and replay. Posted and
completion buffers allow the PEB383 to accept a few more cycles of data transfer even after the
assertion of stall which indicates to the initiator in the PCI Core to stop the data transfer. This buffer
design ensures idle cycles are not inserted in data cycles while forwarding TLPs to its egress block.