14. Register Descriptions > PCIe Capability Registers
180
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
14.6.4
PCIe Link Capabilities Register
Register name: PCIE_LNK_CAP
Reset value: 0x0001_3C11
Register offset: 0x0CC
Bits
7
6
5
4
3
2
1
0
31:24
PORT_NUM
23:16
Reserved
DLL_LNK_
ACT_REP_
CAP
SRP_DWN
_ERR_REP
_CAP
CLK_PWR_
MGT
L1_EXIT
15:08
L1_EXIT
L0S_EXIT
ASPM
MAX_WIDTH
07:00
MAX_WIDTH
MAX_SPEED
Bits
Name
Description
Type
Reset value
31:24
PORT_NUM
PCIe Port Number
The PEB383 always reports a port number of 0 for this field.
R
0x00
23:21
Reserved
PCIe Reserved. This field always reads 0.
R
0x00
20
DLL_LNK_ACT_
REP_CAP
Data Link Layer Link Active Reporting Capable
For a downstream port, this bit must be set to 1 if the
component can report the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug
capable downstream port, this bit must be set to 1.
For upstream ports and components that do not support this
capability, this bit must be hardwired to 0.
Note: The PEB383 does not support
DLL_LNK_ACT_REP_CAP. This field always reads 0.
R
0
19
SRP_DWN_ERR_
REP_CAP
Surprise Down Error Reporting Capable
For a downstream port, this bit must be set to 1 if the
component can detect and report a Surprise Down error
condition.
For upstream ports and components that do not support this
capability, this bit must be hardwired to 0.
Note: The PEB383 does not support
SRP_DWN_ERR_REP_CAP. This field always reads 0.
R
0