15. Electrical Characteristics > AC Timing Specifications
231
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
15.6.5
Boundary Scan Test Signal Timing
The following table lists the test signal timings for the PEB383.
15.6.6
Reset Timing
The following table lists the reset signal timings for the PEB383.
Table 50: Boundary Scan Test Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
T
BSF
JT_TCK Frequency
0
10
MHz
-
T
BSCH
JT_TCK High Time
50
-
ns
Measured at
1.5V,
a
a.
Not tested.
T
BSCL
JT_TCK Low Time
50
-
ns
Measured at
T
BSCR
JT_TCK Rise Time
-
25
ns
0.8V to 2.0V,
T
BSCF
JT_TCK Fall Time
-
25
ns
2.0V to 0.8V,
T
SIS1
Input Setup to JT_TCK
10
-
ns
b
b.
.
T
BSIH1
Input Hold from JT_TCK
10
-
ns
T
BSOV1
JT_TDO Output Valid Delay from falling edge of
JT_TCK.
-
15
ns
c
,
d
c.
Outputs precharged to V
DD33
.
d.
.
T
OF1
JT_TDO Output Float Delay from falling edge of
JT_TCK
-
15
ns
e
e.
A float condition occurs when the output current becomes less than I
LO
. Float delay is not tested (see
).
Table 51: Reset Timing
Symbol
Parameter
Min
Max
Units
Notes
T
POR
Power supplies in recommended
operating range to de-assertion of device
reset
100
-
ms
The PCIe specification
requires reset
(PCIE_PERSTn) to
remain asserted for
100 ms after power
supplies are valid.
T
ACTIVE
Reset active time
1
-
ms
-