2. Signal Descriptions > Power Supply Signals
20
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required
2.7
Power Supply Signals
Table 7: Power Supply Signals
Name
Pin Type
Description
Design Recommendation
a
a.
For filtering and decoupling information for these signals, see “Power Supply Filtering and Decoupling” in the
PEB383 Board
Design Guidelines
.
VDD
Core power
1.05V core power
None.
VDD_PCI
I/O power
3.3 volt I/O power for PCI and 3.3V I/O
power for CMOS
None.
VDD_PCIE
Core power
1.05V power for SerDes
Connect these signals to the 1.05V
source through a ferrite bead.
b
b.
For more information, see “Analog Power Supply Filtering” in the
PEB383 Board Design Guidelines
.
VDDA_PCIE
Analog power
3.3V analog power for SerDes
Connect these signals to the 3.3V
source through a ferrite bead.
VDDA_PLL
Analog power
1.05V analog power for PLL
Connect these signals to the 1.05V
source through a ferrite bead.
VIO_PCI
I/O power
5.0 I/O power, for 5.0V I/O compliance.
This signal can also be tied to 3.3V if
5.0V compliance is not required.
Connect these signals to a 3.3V or 5V
source depending on the PCI devices
attached to the PEB383 PCI bus.
VSS
GND
GND, core power
None.
VSS_IO
GND
GND, I/O power
None.
VSSA_PLL
GND
GND, analog PLL power
None.