IDT 89HPES12N3 User Manual Download

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Notes

PES12N3 User Manual

vii

June 7, 2006

List of Figures

Figure 1.1

PES12N3 Functional Block Diagram ................................................................................ 1-2

Figure 1.2

PES12N3 Architectural Block Diagram ............................................................................. 1-3

Figure 1.3

PES12N3 Logic Diagram .................................................................................................. 1-6

Figure 2.1

Fundamental Reset in Transparent Mode with Serial EEPROM initialization ................... 2-6

Figure 3.1

Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[1:0]=0x2) ....................... 3-2

Figure 3.2

Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[1:0]=0x1) ....................... 3-2

Figure 4.1

PES12N3 Switch Data Flow and Buffering ....................................................................... 4-1

Figure 5.1

PES12N3 Power Management State Transition Diagram ................................................ 5-1

Figure 5.2

PES12N3 ASPM Link Sate Transitions ............................................................................ 5-3

Figure 6.1

Hot-Plug on Switch Downstream Slots Application ........................................................... 6-1

Figure 6.2

Hot-Plug with Switch on Add-In Card Application ............................................................. 6-2

Figure 6.3

Hot-Plug with Carrier Card Application ............................................................................. 6-2

Figure 7.1

SMBus Interface Configuration Examples ........................................................................ 7-1

Figure 7.2

Single Double Word Initialization Sequence Format ......................................................... 7-6

Figure 7.3

Sequential Double Word Initialization Sequence Format .................................................. 7-6

Figure 7.4

Configuration Done Sequence Format ............................................................................. 7-7

Figure 7.5

Slave SMBus Command Code Format ............................................................................. 7-9

Figure 7.6

CSR Register Read or Write CMD Field Format ............................................................. 7-11

Figure 7.7

Serial EEPROM Read or Write CMD Field Format ......................................................... 7-12

Figure 7.8

CSR Register Read Using SMBus Block Write/Read Transactions
with PEC Disabled .......................................................................................................... 7-13

Figure 7.9

Serial EEPROM Read Using SMBus Block Write/Read Transactions
with PEC Disabled .......................................................................................................... 7-14

Figure 7.10

CSR Register Write Using SMBus Block Write Transactions with PEC Disabled .......... 7-14

Figure 7.11

Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ....... 7-14

Figure 7.12

Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ....... 7-14

Figure 7.13

CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ... 7-15

Figure 9.1

PES12N3 Functional Block Diagram in Transparent Mode .............................................. 9-1

Figure 9.2

Port Configuration Space Organization ............................................................................ 9-7