Notes
PES12N3 User Manual
11 - 1
June 7, 2006
Chapter 11
JTAG Boundary Scan
Introduction
The JTAG Boundary Scan interface provides a way to test the interconnections between integrated
circuit pins after they have been assembled onto a circuit board.
There are two pin types present in the PES12N3: AC-coupled and DC-coupled (also called AC and DC
pins). The Boundary Scan interface in the PES12N3 is both IEEE 1149.1 and 1149.6 compliant to allow
simultaneous testing of both AC and DC pins. The DC pins are those “normal” pins that do not require AC-
coupling and are tested in the PES12N3 using the IEEE 1149.1 standard.
The presence of AC-coupling capacitors on some of the PES12N3 pins prevents DC values from being
driven between a driver and receiver. An AC Boundary Scan methodology, as described in IEEE 1149.6, is
available to provide a time-varying signal to pass through the AC-coupling when in AC test mode.
Test Access Point
The system logic utilizes a 16-state, six-bit TAP controller, a four-bit instruction register, and five dedi-
cated pins to perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to
allow the five external JTAG control pins to control and access the PES12N3's many external signal pins.
The JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the
PES12N3 is depicted in Figure 11.1.
Figure 11.1 Diagram of the JTAG Logic
Refer to the IEEE 1149.1 and 1149.6 documents for a complete operational description of the Boundary
Scan and TAP controller.
Signal Definitions
JTAG operations such as reset, state-transition control, and clock sampling are handled through the
signals listed in Table 11.1. A functional overview of the TAP Controller and Boundary Scan registers is
provided in the sections following the table.
Bypass Register
Instruction Register Decoder
4-Bit Instruction Register
Tap Controller
m
u
x
m
u
x
Device ID Register
Boundary Scan Register
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TRST_N
JTAG_TDO
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
