IDT JTAG Boundary Scan
Test Data Register (DR)
PES12N3 User Manual
11 - 4
June 7, 2006
Notes
Test Data Register (DR)
The Test Data register contains the following:
Bypass register
Boundary Scan registers
Device ID register
These registers are connected in parallel between a common serial input and a common serial data
output and are described in the following sections. For more detailed descriptions, refer to IEEE Standard
Test Access Port (IEEE Std. 1149.1).
Boundary Scan Registers
This boundary scan chain is connected between JTAG_TDI and JTAG_TDO when EXTEST or
SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes
through the UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output
latches is immediately transferred to the corresponding outputs or output enables.
Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the
boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the
boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor-
rect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is
shown in Figure 11.3.
Figure 11.3 Diagram of Observe-only Input Cell
The simplified logic configuration of the output cells is shown in Figure 11.4.
Input
Pin
shift_dr
From previous cell
clock_dr
D
Q
To next cell
To core logic
MUX
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Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
