Notes
PES12N3 User Manual
1 - 1
June 7, 2006
Chapter 1
PES12N3 Device Overview
Introduction
The 89HPES12N3 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions
offering the next-generation I/O interconnect standard. The PES12N3 is a 12 lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized for high performance applications
such as servers, storage, and communications/networking. It provides high-performance I/O connectivity
and switching functions between a PCI Express upstream port and two downstream ports or peer-to-peer
switching between downstream ports.
Utilizing standard PCI Express interconnect, the PES12N3 provides the most efficient high-performance
I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 6 GBps (48 Gbps) of aggregate switching capacity
through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of
bandwidth in both directions. The PES12N3 is fully compliant with PCI Express Base specification 1.0a.
The PES12N3 is based on a flexible and efficient layered architecture. The PCI Express layer consists
of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12N3 can operate either as a store and forward or cut-through switch and is
designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management. This includes system selectable algorithms such
as round robin and weighted round-robin schemes guaranteeing bandwidth allocation and/or latency for
critical traffic classes in applications such as high throughput 10 Gigabit I/Os, streaming media for graphics,
TV tuners, and cameras.
Figure 1.1 provides a functional block diagram while Figure 1.2 illustrates the architecture of the device.
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
