Notes
PES12N3 User Manual
1
June 7, 2006
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES12N3, a member of IDT’s
PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan-
dard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES12N3 Device Overview,” provides a complete introduction to the performance capa-
bilities of the 89HPES12N3. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.
Chapter 5, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES12N3.
Chapter 6, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in
the PES12N3.
Chapter 7, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES12N3.
Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions
Chapter 9, “Transparent Mode Operation,” describes how the PES12N3 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.
Chapter 10, “Test and Debug,” discusses the six test modes, in addition to the normal operating mode,
associated with the PES12N3.
Chapter 11, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
