IDT Transparent Mode Operation
Generic PCI to PCI Bridge Register Definition
PES12N3 User Manual
9 - 26
June 7, 2006
Notes
BCTRL - Bridge Control (0x03E)
PCI Express Capability Structure
PCIECAP - PCI Express Capability (0x040)
Bit
Field
Field
Name
Type
Default
Value
Description
0
PERRE
RW
0x0
Parity Error Response Enable. This bit controls the
bridges response to poisoned TLPs on the secondary inter-
face.
0x0 -
(ignore) Ignore poisoned TLPs (i.e., parity errors)
on the secondary interface.
0x1 - (report) Enable poisoned TLP (i.e., parity error)
detection and reporting on the secondary interface
of the bridge.
1
SERRE
RW
0x0
System Error Enable. This bit controls forwarding of
ERR_COR, ERR_NONFATAL, ERR_FATAL from the sec-
ondary interface of the bridge to the primary interface.
Note that error reporting must be enabled in the Command
register or PCI Express Capability structure, Device Con-
trol register for errors to be reported on the primary inter-
face.
0x0 - (ignore) Do not forward errors from the secondary
to the primary interface.
0x1 - (report) Enable forwarding of errors from secondary
to the primary interface.
2
ISAEN
RO
0x0
ISA Enable. The PES12N3 does not support this feature.
3
VGAEN
(for revisions
YA and YB)
RW
0x0
VGA Enable. (Silicon revisions YA and YB only.)
Controls the routing of processor-initiated transactions tar-
geting VGA.
0 -
(block) Do not forward VGA compatible addresses
from the primary interface to the secondary inter-
face
1 -
(forward) Forward VGA compatible addresses from
the primary to the secondary interface.
VGAEN
(for revision YC)
RO
0x0
Silicon revision YC does not support the VGA Enable fea-
ture.
5:4
Reserved
RO
0x0
6
SRESET
RW
0x0
Secondary Bus Reset. Setting this bit triggers a hot reset
down the secondary interface of the bridge.
15:7
Reserved
RO
0x0
Bit
Field
Field
Name
Type
Default
Value
Description
7:0
CAPID
RO
0x10
Capability ID. The value of 0x10 identifies this capability
as a PCI Express capability structure.
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...