IDT Test and Debug
Device Test Modes
PES12N3 User Manual
10 - 2
June 7, 2006
Notes
Internal Pseudo Random Bit Stream Self-Test Test Mode (SWMODE[3:0]
= 0xA)
In the Internal Pseudo Random Bit Stream Self-test Test mode, a pseudo random bit stream is gener-
ated, looped back internally through the SerDes, and checked. This mode is graphically illustrated in Figure
10.2.
Figure 10.2 Internal Pseudo Random Bit Stream Self-Test
After reset, all 24-lanes of the device enter this test mode. However, individual lanes may be enabled
and disabled by setting/clearing bits in the PAEN, PBEN and PCEN fields in the port A Test Mode Control
(PA_TMCTL) register. When this test mode is entered, the PRBS generator sends 1024 STP symbols
followed by a 127 bit PRBS sequence. Once the sequence completes, the entire process repeats.
The PRBS sequence is generated by a 7-bit LFSR with primitive polynomial x
6
+ x + 1 initialized to all
ones. The operation of the PRBS is equivalent to a PRBS operating at the SerDes bit clock followed by a
10-bit shift register. The 10-bit symbol produced is the output of this shift register every 10 bit clocks. The
first 10 symbols produced in the PRBS sequence are shown in Table 10.1.
When this test mode is entered, the PRBS checker receives and discards STP symbols. This is referred
to as PRBS synchronization. After 64 STP symbols are received, the PRBS checker is said to have
achieved synchronization and the corresponding bit in the PASA, PBSA or PCSA field in the port A Test
Mode Synchronization Status (PA_TMSSTS) register is set.
The first non-STP symbol received after synchronization has been achieved is assumed to be the first
symbol of the PRBS sequence. This value is checked against the expected value. If a mismatch is found,
the corresponding bit in the PATF, PBTF or PCTF field of the port A Test Mode Fail Status (PA_TMFSTS)
register is set.
Symbol
Number
Symbol
1
0b0000001000
2
0b0011000010
3
0b1000111100
4
0b1000101100
5
0b1110101001
6
0b1111010000
7
0b1110001001
8
0b0011011010
9
0b1101111011
10
0b0001101001
Table 10.1 PRBS LFSR Symbol Output
Ser
D
es
PES12N3
10b
PRBS Gen.
PRBS Check
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
