IDT PES12N3 Device Overview
Pin Description
PES12N3 User Manual
1 - 7
June 7, 2006
Notes
Pin Description
The following tables lists the functions of the pins provided on the PES12N3. Some of the functions
listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being
active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select
lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PEALREV
I
PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port A are reversed. This value may be overridden by modify-
ing the value of the PALREV bit in the PA_SWCTL register.
PEARP[3:0]
PEARN[3:0]
I
PCI Express Port A Serial Data Receive. Differential PCI Express receive
pairs for port A.
PEATP[3:0]
PEATN[3:0
O
PCI Express Port A Serial Data Transmit. Differential PCI Express trans-
mit pairs for port A
PEBLREV
I
PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port B are reversed. This value may be overridden by modify-
ing the value of the PBLREV bit in the PA_SWCTL register.
PEBRP[3:0]
PEBRN[3:0]
I
PCI Express Port B Serial Data Receive. Differential PCI Express receive
pairs for port B.
PEBTP[3:0]
PEBTN[3:0]
O
PCI Express Port B Serial Data Transmit. Differential PCI Express trans-
mit pairs for port B
PECLREV
I
PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of
PCI Express Port C are reversed. This value may be overridden by modify-
ing the value of the PCLREV bit in the PA_SWCTL register.
PECRP[3:0]
PECRN[3:0]
I
PCI Express Port C Serial Data Receive. Differential PCI Express receive
pairs for port C.
PECTP[3:0]
PECTN[3:0]
O
PCI Express Port C Serial Data Transmit. Differential PCI Express trans-
mit pairs for port C
REFCLKP[1:0]
REFCLKN[1:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. These signals select the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 1.3 PCI Express Interface Pins
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
