IDT Clocking, Reset, and Initialization
Reset
PES12N3 User Manual
2 - 6
June 7, 2006
Notes
PA_SMBUSSTS register is set.
12. Wait for link training on all ports to complete or fail.
1
13. If the Reset Halt (RSTHALT) bit is set in the PA_SWCTL register, all of the logic is held in a reset
state except the master and slave SMBuses, the control/status registers, and the stacks which
continue to be held in a quasi-reset state and respond to configuration transactions with a retry. The
device remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an
external agent may read and write any internal control and status registers and may access the
external serial EEPROM via the PA_EEPROMINTF register.
14. Normal device operation begins.
The PCIe® standard specifies that normal operation should begin within 1.0 second after a fundamental
reset of a device. The reset sequence above guarantees that normal operation will begin within this period
as long as the serial EEPROM initialization process completes within 200 ms. Under normal circumstances,
200 ms is more than adequate to initialize every register in the device even with a Master SMBus operating
frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
The operation of a fundamental reset in Transparent mode with serial EEPROM initialization (i.e.,
SWMODE[3:0] = 0x1) is illustrated in Figure 2.1.
Figure 2.1 Fundamental Reset in Transparent Mode with Serial EEPROM initialization
Hot Reset
A hot reset may be initiated globally to the entire device, globally to downstream ports or locally to down-
stream port(s).
Globally Initiated Hot Reset To Entire Device
A hot reset is initiated globally to the entire device when any of the following conditions occur.
–
Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
–
Data link layer of the upstream port transitions to the DL_Down state.
1.
While link training is in progress, a stack responds to configuration retry requests with a configuration request
retry status completion and ignores all other transactions. This process stops when link training successfully
completes, a device is not detected on the link, or when link training fails 16 times.
REFCLK*
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
RSTHALT
Tpvperl
PLL Reset and Lock
CDR Reset & Lock
Ready for Normal Operation
Ready
Ready
Serial EEPROM Initialization
* Clock not shown to scale
1.01 ms
up to 12 µs
Link Training
Quasi Reset Mode
Ready for Normal Operation
< 100 ms
Boot vector sampled
Device ready for
normal operation
< 1 sec
Stacks
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
