IDT 89HPES12N3 User Manual Download

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Notes

PES12N3 User Manual

3 - 1

June 7, 2006

Chapter 3

Link Operation

Introduction

The PES12N3 contains three ports. The default link width of each port is x4 and the SerDes lanes are

statically assigned to a port.

Polarity Inversion

Each port of the PES12N3 supports automatic polarity inversion as required by the PCIe® specification.

Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its data.
During link training, the receiver examines symbols six through 16 of the TS1 and TS2 ordered sets for
inversion of the PExAP[n] and PExAN[n] signals. If an inversion is detected, then logic for the receiving lane
automatically inverts received data.

Polarity inversion is a lane and not a link function. Therefore, it is possible for some lanes of link to be

inverted and for others to not be inverted.

Link Width Negotiation

The PES12N3 supports the option link variable width negotiation feature outlined in the PCIe specifica-

tion. During link training, Each of the x4 ports is capable of negotiating to a x4, x2 or x1 link width. The
negotiated width of each link may be determined from the Link Width (LW) field in the corresponding port’s
PCI Express® Link Status (PCIELSTS) register.

The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP)

register contains the maximum link width of the port. This field is of RWL type and may be modified when
the REGUNLOCK bit is set in the PA_SWCTL register. Modification of this field allows the maximum link
width of the port to be configured. The new link width takes effect the next time link training occurs.

To force a link width to x2 despite a link partner’s ability to negotiate to x4, the MAXLNKWDTH field

could be configured through Serial EEPROM initialization and link retraining forced. Assuming the link
partner has a link width greater than or equal to x2 and the capability to negotiate to a width of x2, the link
width will negotiate to x2.

When a link negotiates to a width less than x4, the unused lanes are put in a low power state (i.e. L1

state).

Lane Reversal

The PCIe specification describes an optional lane reversal feature. The PES12N3 does not support the

automatic lane reversal feature outlined in the PCIe specification. However, it does support static lane
reversal on a per port basis.

Associated with each PES12N3 switch port is a lane reversal signal. The lane reversal signal for port A

is PEALREV, for port B is PEBLREV, and port C is PECLREV. The status of the lane reversal signals
sampled during a fundamental reset may be determined from the PALREV, PBLREV and PCLREV fields in
the PA_SWSTS register.

The port lane reversal signals are sampled during a fundamental reset and used as the initial value of

the PALREV, PBLREV and PCLREV fields in the PA_SWCTL register. When these bits are set, then the
lanes of the corresponding port(s) are reversed during link training.

Lane reversal mapping for the various non-trivial maximum link width configurations is illustrated in

Figures 3.1 and 3.2.