IDT 89HPES12N3 User Manual Download

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IDT Switch Operation

Switch Core Errors

PES12N3 User Manual

4 - 8

June 7, 2006

Notes

If a Downstream Port goes to DL_Down status, the INTx virtual wires associated with that port are deas-

serted, and the port A aggregates are updated accordingly. This may result in the upstream port generating
a Deassert_Intx message.

Switch Core Errors

This section lists error conditions that are checked by the switch core. Due to limited buffering of Unsup-

ported Request (UR) completions, it is possible for the PES12N3 to discard UR completions if errors are
generated faster than UR completions can be transmitted. Even when UR completions are discarded, error
status bits are always correctly updated and an error message is generated.

Due to limited buffering, error messages may be collapsed if errors are generated faster than error

messages can be transmitted. This means that multiple error conditions may result in only a single error
message being generated. However, under no circumstances are error messages discarded.

Port arbitration should never be configured to starve a port. If a port arbitration table configuration

results in port starvation, then TLPs generated by the port may be dropped (e.g., error messages, inter-
rupts, configuration completions, etc.).

The following events received by the switch core from the upstream port are treated as Unsupported

Requests (UR), and for non-posted transactions, result in a Unsupported Request (UR) completion being
returned to the upstream port.

–

Reception of a CfgRd0 or CfgWr0 TLP. All CfgRd0 and CfgWr0 TLPs should have been received
and processed by the upstream stack. Therefore, the upstream stack should never pass a CfgRd0
or CfgWr0 to the switch core.

–

Reception of a CfgRd1 or CfgWr1 TLP that is transformed into a CfgRd0 or CfgWr0 TLP destined
to the link partner of a downstream port and in which the device number is non-zero (covers condi-
tion outlined in PCIe base 1.0a Section 7.3.1). The device number must be zero in CfgRd0 and
CfgWr0 transactions to a downstream link partner.

–

Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI
bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.

–

Reception of route by address TLPs whose address matches an upstream port’s memory or I/O
base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.

–

Reception of route by address TLPs destined to the upstream port. There are no route by address
TLPs that should have been destined to the upstream port since the upstream port does not
process these types of TLPs.

Port A Interrupt

Interrupt Sources

Port X INTy corresponds to external downstream generated INTy interrupts and hot-

plug INTy interrupts generated by the port.

INTA

Port B INTA

Port C INTD

INTB

Port B INTB
Port C INTA

INTC

Port B INTC
Port C INTB

INTD