12. Register Descriptions
265
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com
EIM
R/W
P1_RST
0
ENUM# Signal Mask
1 = Mask Signal
0 = Enable Signal
NXT_PTR [7:0]
R
P1_RST
0xE8 or 0
Next Pointer
If VPD_EN bit is set in the
“Miscellaneous Control and Status
and an external EEPROM is detected,
then this field reads back 0xE8. When the VPD_EN bit in the
MISC_CSR register is cleared or an external EEPROM is not
detected, this field reads back 0.
CAP_ID [7:0]
R
P1_RST
0x06
Capability ID
Name
Type
Reset
By
Reset
State
Function