Industrial Electronic Engineers, Inc.
SIZE
A
CODE IDENT
NO.
05464
S03858–06–0105
Van Nuys, California
Scale: NONE
Rev C
Sheet 15
4.5
Timing Sequence for 8 Bit Parallel Interface
Figure 13 illustrates the typical Busy Flag check sequence for an 8 bit data interface.
Figure 13
Busy Flag Check Sequence for 8–bit Parallel Interface
4.6
Timing Sequence for 4 Bit Parallel Interface
Figure 14 illustrates the typical Busy Flag check sequence for a 4 bit data bus interface.
Figure 14
Busy Flag Check Sequence for 4–bit Parallel Interface
Note: IR
7
, IR
3
:
Instruction, 7th bit & 3rd bit
AC
3
:
Address Counter, 3rd bit
Data
Busy
Busy
IR 7
Not
Busy
Internal Operation
Instruction
Write
Instruction
Write
Busy Flag
Check
Busy Flag
Check
Busy Flag
Check
DB7
Internal
E
R/W
RS
DB
IR
7
IR
7
IR
3
AC
3
D
3
AC
3
Busy
Not
Busy
7
Internal Operation
E
RS
Instruction
Write
Busy Flag
Check
Busy Flag
Check
Instruction
Write