WAFER-ULT3/ULT4 3.5" SBC
Page 75
Î
All
D
EFAULT
Enable all cores in the processor package.
Î
1
Enable one core in the processor package.
Î
Hyper-threading [Enabled]
Use the
Hyper-threading
BIOS option to enable or disable the Intel Hyper-Threading
Technology.
Î
Disabled
Disables the Intel Hyper-Threading Technology.
Î
Enabled D
EFAULT
Enables the Intel Hyper-Threading Technology.
Î
Intel
®
SpeedStep™ [Enabled]
Use the
Intel
®
SpeedStep™
option to enable or disable the Intel
®
SpeedStep
Technology.
Î
Disabled
Disables the Intel
®
SpeedStep Technology.
Î
Enabled D
EFAULT
Enables the Intel
®
SpeedStep Technology.
Î
C State [Disabled]
Use the
C State
option to enable or disable CPU C state.
Î
Disabled D
EFAULT
Disables CPU C state.
Î
Enabled
Enables CPU C state.
Summary of Contents for WAFER-UTL3
Page 14: ...WAFER ULT3 ULT4 3 5 SBC Page 1 Chapter 1 1 Introduction...
Page 18: ...WAFER ULT3 ULT4 3 5 SBC Page 5 Figure 1 3 Connectors Solder Side...
Page 24: ...WAFER ULT3 ULT4 3 5 SBC Page 11 Chapter 2 2 Packing List...
Page 28: ...WAFER ULT3 ULT4 3 5 SBC Page 15 Chapter 3 3 Connectors...
Page 59: ...WAFER ULT3 ULT4 3 5 SBC Page 46 Chapter 4 4 Installation...
Page 82: ...WAFER ULT3 ULT4 3 5 SBC Page 69 Chapter 5 5 BIOS...
Page 117: ...WAFER ULT3 ULT4 3 5 SBC Page 104 Appendix A A Regulatory Compliance...
Page 119: ...WAFER ULT3 ULT4 3 5 SBC Page 106 Appendix B B BIOS Options...
Page 122: ...WAFER ULT3 ULT4 3 5 SBC Page 109 Appendix C C Terminology...
Page 126: ...WAFER ULT3 ULT4 3 5 SBC Page 113 Appendix D D Digital I O Interface...
Page 129: ...WAFER ULT3 ULT4 3 5 SBC Page 116 Appendix E E Watchdog Timer...
Page 132: ...WAFER ULT3 ULT4 3 5 SBC Page 119 Appendix F F Hazardous Materials Disclosure...