R E M O T E O P E R A T I O N
Status Reporting
7/01
MPS-8033
27
C H A P T E R
3
!
Register Structure and Contents
This section provides information about the structure and contents of the different internal registers.
Condition Status Register Pair
Condition Status is a 16−bit register/enable−register pair with this structure:
Bit Reference:
The Condition Status Enable Register allows you to control which events in the Condition Status
Register can set bit 3 in the status byte register. Note that this register pair is identical to the Event
Status register pair (above), except for bit 11.
Conditions reflect the current state of the 8033, and so may change often. Querying the Condition
Status Register does NOT change its contents.
Related commands: (See Chapter 4, Command Reference for details).
•
*COND?
˙Query the contents of the Condition Status Register.
•
*ENABle:COND <nrf>
˙Set an enable mask in the Condition Status Enable Register.
•
*ENABle:COND?
˙Query the Condition Status Enable Register mask settings.
0− Output On
4− N/A
8− N/A
12− Calculation Error
1− Interlock Disabled
5− N/A
9− N/A
13− Hardware Error
2− N/A
6− N/A
10− N/A
14− Software Error
3− N/A
7− N/A
11− Cal Ready
15− Checksum Error
&
&
&
&
&
&
&
&
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
&
&
&
&
&
&
&
&
15 14131211 10
8
9
10
11
12
13
14
15
9 8
Copy of Status Byte
Parallel Poll Enable Register
Logical
OR
IST TRUE
Condition Status Register
Condition Status Enable Register
To Bit 1, Status Byte Register
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Summary of Contents for MPS-8033 Series
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