R E M O T E O P E R A T I O N
Status Reporting
30
MPS-8033
C H A P T E R
3
!
Status Byte and Service Request Enable Register
The Service Request Enable Register is logically ANDed to the Status Byte. If the result is non−zero,
then bit #6 of the Status Byte is set to 1, and an SRQ interrupt is initiated.
Status Byte and Service Request Enable Register Pair are 8−bit registers with this structure:
Device Dependent Event and Condition Registers
The Event Registers are used to report events which occur during the operation of the 8033. Events
differ from conditions in that events signal an occurrence once, and are not reset until the Event
Register is queried or the 8033 is powered off. Conditions reflect the current state of the device, and
therefore may change many times during operation. Querying a Condition Register does not
change its contents.
Operation Complete Definition
Note that bit #0 of the Standard Event Status Register contains the Operation Complete flag. This
bit may be used to signal an SRQ to the controlling software for more efficient, interrupt driven
software. Enable the SRQ by setting bit #0 in the Standard Event Status Enable Register (*ESE)
and bit #5 in the Service Request Enable Register (*SRE). This may be used to initiate service
request routines which depend on the completion of all previous commands.
The following conditions define "Operation Complete" within the 8033:
•
The controller, which is updating the hardware, is idle.
•
No NVRAM (non−volatile random access memory) write cycles are in progress.
•
No calibration routines are running.
•
The output is off, or
•
The output is on and the output−on delay period has finished.
7 6
3 2 1 0
7
5 4 3 2 1 0
&
&
&
&
&
&
&
Logical OR
Status Byte
Service Request Enable Register
5 4
Service
Request
(SRQ)
Event Summary
Condition Summary
Not Used
Not Used
(MAV) Message Available
Error Queue Not Empty
Standard Event Summary (ESB)
True
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Summary of Contents for MPS-8033 Series
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