C O M M A N D R E F E R E N C E
GPIB Command Reference
7/01
MPS-8033
65
C H A P T E R
4
!
Action
Determines the contents of the PARALLEL POLL ENABLE REGISTER.
Response
The value must be between 0 and 65535. Binary Integer Sum of:
Action
Sets automatic power−on clearing of the enable registers.
Values
0 = disable power−on clearing
1 = enable power−on clearing
Notes
Any non−zero value is interpreted as 1.
Registers affected:
Condition Status Enable
Service Request Enable
Event Status Enable
Standard Event Status Enable
Factory default condition: disabled.
In the disabled state, the values of the enable registers are saved through power OFF/ON. The
power−on status clear flag (see PSC?) is set false, disallowing service request interrupts after
power−on.
In the enabled state, the enable registers are cleared during power ON. The power−on status clear
flag (see PSC?) is set true, allowing service request interrupts after power−on.
Examples
*PSC 0
Disable automatic power−on clearing of the enable registers.
*PSC 1
Enable automatic power−on clearing of the enable registers.
*PRE?
C
OMMON
D
EVICE
D
EPENDENT
F
RONT
P
ANEL
*PSC <nrf value>
Power−on Status Clear
C
OMMON
D
EVICE
D
EPENDENT
F
RONT
P
ANEL
*PSC?
Power−on Status Clear?
C
OMMON
D
EVICE
D
EPENDENT
F
RONT
P
ANEL
&
&
&
&
&
&
&
&
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
&
&
&
&
&
&
&
&
15 14131211 10
8
9
10
11
12
13
14
15
9 8
Copy of Status Byte
Parallel Poll Enable Register
Logical
OR
IST TRUE
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Summary of Contents for MPS-8033 Series
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