XC2200 Derivatives
System Units (Vol. 1 of 2)
Memory Organization
User’s Manual
3-22
V2.1, 2008-08
MemoryX2K, V1.3
3.9.3
Operations
The flash memory supports the following operations:
•
Instruction fetch.
•
Data read.
•
Command sequences to change data and control the protection.
3.9.3.1
Instruction Fetch from Flash Memory
Instructions are fetched by the PMU in groups of aligned 64 bits. These code requests
are forwarded to the flash memory. It needs a varying number of cycles (depending on
the system clock frequency) to perform the read access. The number of cycles must be
known to the IMB Core because the flash does not signal data availability. The number
of wait-cycles is therefore stored in the
register.
One read access to the flash memory delivers 128 data bits and a 9-bit ECC value. The
ECC value is used to detect and possibly correct errors. The addressed 64-bit part of the
128-bit chunk is sent to the PMU. The complete 128 data bits and the 9 ECC bits are
stored in the IMB Core with their address. If a succeeding fetch request matches this
address the data is delivered from the buffer without performing a read access in the
flash memory. The delivery from the buffer happens after one cycle. The flash read wait-
cycles are not waited.
The stored data are a kind of instruction cache. In order to support self-modifying code
(e.g. boot loaders) this cache is invalidated when the corresponding address is written
(i.e. erased or programmed).
In addition to this fetch buffer the IMB Core has an additional performance increasing
feature — the Linear Code Pre-Fetch. When this feature is enabled with
.DLCPF = 0 the IMB Core fetches autonomously the following
instructions while the CPU executes from its own buffers or the fetch buffer. As this
feature is fetching only the linear successors (it does not analyze the code stream) it is
most effective for code with longer linear sequences. For code with a high density of
jumps and calls it can even cause a reduction of performance and should be switched
off.
