Infineon ISOFACE ISO2H823V2, Manual

Page 1: ...different kind of loads can be connected at a 2 row 8 output terminal connector The board is intended to demonstrate the capabilities of the ISO2H823V2 5 Internet Presence http www infineon com isoface Order Information EVAL ISO2H823V2 5 Attention The focus is safe operation under evaluation conditions The board is neither cost nor size optimized and does not serve as a reference design 1 Overview...

Page 2: ...Application Note 2 2015 02 11 Revision 1 0 ISO2H823V2 5 Evaluation Board Board Manual About this document 5 1 Schematic 22 5 2 Components Placement 23 5 3 Layout 24 5 4 Bill of Material 26 ...

Page 3: ...The power chip generates out of VBB two internal voltages VDDIO 3 3 V 10 and VCORE 1 5 V 10 which have to be buffered externally The ISOFACE ISO2H823V2 5 includes 8 high side power switches that are controlled by means of the integrated parallel serial interface The interface is 8 bit µController compatible Furthermore a direct control mode can be selected that allows the direct control of the out...

Page 4: ...r fault indication Supply connector 24V VBB 2x8 pin terminal for load connection LED Matrix indicating the output status Figure 2 ISO2H823V2 5 Evaluation Board Revision 1 1 Table 1 Board Characteristics Parameter Min Max Unit Remarks VDD 3V3 Input Voltage 3 0 3 8 V Supply for the control side of the IC either supplied via connector X1 or connector pin 2 of connector SV1 VBB 24V Input Voltage 11 35...

Page 5: ...e connector SV1 with 3 3V The process side can be powered via the 2 pin terminal X2 with 24V nominal 2 2 Microcontroller Interface The ISO2H823V2 5 contains a microcontroller interface which can be configured as a parallel or serial interface via the SEL pin SEL Serial or Parallel Mode Select When this pin is in a logic Low state the IC operates in parallel mode For serial mode operation the pin h...

Page 6: ...dge of WR The AD7 bit of the register address has to be set to 1 This pin has an internal Pull Up resistor RD Read By pulling this pin down a read transaction is initiated on the AddressData bus and the data are driven by the falling edge of RD The AD7 bit of the register address has to be set to 0 This pin has an internal Pull Up resistor ALE Address Latch Enable The pin ALE is used to select bet...

Page 7: ...tics in the ISO2H823V2 5 datasheet Figure 4 Timing by Parallel Read Access e g GLERR Register For a reading access to internal registers the MSB of the address register has to be set to 0 VCC CS WR AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 MCU e g XMCxxxx or ASIC ISO2H823V2 parallel _interface_iso2h823 vsd VCC ALE SEL RD rd_timing_ifx uc_parallel CS AD 7 0 tADout ALE RD tAD_hd tRDlow tRDhigh tRD_su tfloat t...

Page 8: ...lel Write Access e g DRIVE Register For a writing access to internal registers the MSB of the address register has to be set to 1 wr_timing_ifx uc_parallel CS AD 7 0 ALE WR tAD_hd tWRhigh tWR_su tWR_hd tlat DRIVE DRIVE address 80h tAD_su DRIVE data 0Fh tAD_hd tAD_su DRIVE data 0Ah 00h 0Fh tCSD OUT 7 0 0Fh 00h tWRlow tCS_ALE tALE_high ...

Page 9: ...n in the Figure 6 The asynchronous output disable ODIS has to be tied high because this safety function will otherwise override the drive information Although the diagnostics cannot be read in this operation mode W4P Wait for power and OTC over temperature faults are reported at the ERR pin volatile Figure 6 Parallel Direct Mode The direct mode is intended to be an additional parallel mode which i...

Page 10: ...ure 8 Figure 9 Figure 10 Figure 11 With every falling edge of SCLK the bits to be read are provided serially to the pin SDO The timing requirements for the serial interface are shown in Figure 7 and inside the chapter electrical characteristics in the ISO2H823V2 5 datasheet Figure 7 Serial Bus Timing 2 2 2 1 SPI Modes Four different SPI modes can be distinguished Figure 8 Figure 11 Figure 8 SPI Mo...

Page 11: ...C3 C2 C1 C0 CD7 CD6 CD5 CD4 CD3 CD1 CD0 CD2 DR6 DR5 DR4 DR3 DR2 DR1 DR0 C4 C3 C2 C1 C0 SCLK SDI CS SDO uc_spi_mode 2 vsd A6 A5 A4 A3 A2 A1 A0 d c Register Address R W D7 D6 D5 D4 D3 D2 D1 D0 R Read 0 Value dont care Value Read MSB LSB MSB LSB Collective Diagnosis Bit15 Bit8 Bit7 Bit0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Register Address R W W Write 1 Value Write MSB LSB MSB LSB Collective ...

Page 12: ...utput current to the current limit value in case of overload The electrical operation point does not lead to a shutdown The excess power dissipation in the power transistor during current limitation will lead to a rapid increase of the junction temperature When the junction temperature exceeds 150 C typ the output will switch off and will switch on again when the junction temperature has cooled do...

Page 13: ... the power transistor is driven down when the drain source voltage drops below a certain limit low load condition The voltage drop across the remaining part is used to evaluate an open load diagnostic Diagnostic Functions For each of the output stages 5 different types of diagnostics are available Table 3 specifies the diagnostics Some of the diagnostics are available only in active mode others on...

Page 14: ...ead to thermal shutdown ALLOFF all drivers in the power chip are disabled by DRIVE programming ODIS setting or temperature shutdown of all channels LAMP the load of one of the drivers behaves like a cold lamp Diagnostics Overview ISO2H823V vsd Output Driver Control Unit OUTx Current Limitation TemperatureSensor Zener Clamping Demag of Induct Loads Protection Unit OLADJ IADJ Diagnostic Unit Short t...

Page 15: ... register is set High The IC operates normally VBB Missing Voltage If the voltage further drops below the MV threshold lower than the previous threshold the MV bit in the GLERR register is set the Power Side of the IC is turned off when reaching the VReset threshold whereas the Micro Controller Side remains active Note The driver stage is self protected in overload condition the internal switches ...

Page 16: ...of the switching perfomance the parallel direct mode will be the first choice 3 1 Setting up the board for the parallel mode Follow the steps before powering up the board Connect Jumper JP3 to GND Connection 2 3 Remove Jumper on JP1 and JP2 if present Ensure that the following signal levels are present at connector SV1 from your control board CS WR RD ODIS SYNC AD0 AD7 Figure 14 Jumper setting for...

Page 17: ...ND Connection 2 3 Remove Jumper on JP1 and JP2 if present Connect your controller to connector SV1 Ensure that the following signal levels are present at SV1 CS set to LOW WR set to LOW RD set to HIGH ALE set to LOW ODIS set to HIGH SYNC set to HIGH After applying VDD and VBB to the board the ERR LED will be turned off The outputs OUT0 OUT7 will be directly controlled via the signals connected to ...

Page 18: ...u are planing to externally control the serial mode Ensure that the following signal levels are present from your control board CS MS0 MS1 ODIS SYNC SDI SDO SCLK CRCERR Figure 15 Jumper setting for serial access If it is not intended to change the used SPI transfer mode by the attached controller the SPI Mode can be set by placing jumpers JP1 and JP2 according Table 2 As an example the setup for S...

Page 19: ...Application Note 19 2015 02 11 Revision 1 0 ISO2H823V2 5 Evaluation Board Board Manual Getting Started Figure 16 Jumper setting for serial mode 2 Mode Selection Jumper Serial_Mode2 emf ...

Page 20: ...r SV1 Signal Mapping Top View 1 2 GND VDD 3 GND ODIS 4 5 GND SYNC 6 7 GND WR 8 9 GND ALE RST 10 11 GND n c 12 13 GND CS 14 15 GND n c 16 17 GND AD0 18 19 GND AD1 20 21 GND AD2 22 23 GND AD3 24 25 GND AD4 26 27 GND AD5 28 29 GND AD6 30 31 n c AD7 32 33 n c SEL 34 35 n c ERR 36 37 GND MS0 RD 38 39 GND MS1 40 Top View Connector SV1 ...

Page 21: ...ent 2 VDD VDD 4 ODIS ODIS 6 SYNC SYNC 8 WR 10 RST ALE 12 14 CS CS 16 18 SDI AD0 20 AD1 22 AD2 24 AD3 26 CRCERR AD4 28 SCLK AD5 30 AD6 32 SDO AD7 34 SEL SEL 36 ERR ERR 38 MSO RD 40 MS1 Table 5 Connector X3 Mapping No Top Row No Lower Row Comment 1 OUT0 9 GNDBB 2 OUT1 10 GNDBB 3 OUT2 11 GNDBB 4 OUT3 12 GNDBB 5 OUT4 13 GNDBB 6 OUT5 14 GNDBB 7 OUT6 15 GNDBB 8 OUT7 16 GNDBB ...

Page 22: ... Schematic 0 1230 14 5 6 1 7854 918 1 1 9612 83 4 9 26 00 1 8 9 5 5 2 5 9 87 38 1918 2 85 36 5 39 5129132 196 5 2 39 98 4 0 2 85 61 92 1 6 5 1 9 13 0 0 2 29 9 6 5 1 85 1 7854 918 5 5 1 96 013 918 87 96 13 71 8 36 808 1 2 6 5 1230 142 00 55 91 2 01 10191 2 87 1 1 30 1 1968 9 01419 918 55 91 2 87 8 1 751 4 9 87 1 9 00 39 0 58 59 51 692 87 9615 59 ...

Page 23: ...Application Note 23 2015 02 11 Revision 1 0 ISO2H823V2 5 Evaluation Board Board Manual Production Data 5 2 Components Placement Figure 19 Component Placement ...

Page 24: ...Application Note 24 2015 02 11 Revision 1 0 ISO2H823V2 5 Evaluation Board Board Manual Production Data 5 3 Layout Figure 20 Top Layer L1 Figure 21 Inner Layer L2 ...

Page 25: ...Application Note 25 2015 02 11 Revision 1 0 ISO2H823V2 5 Evaluation Board Board Manual Production Data Figure 22 Inner Layer L3 Figure 23 Bottom Layer L4 ...

Page 26: ...uF 50V C1206 1206 1 8 D1 D2 SPTS0540Z SPTS0540Z SOD123 2 9 D3 SM15T39A TVS 39V 1500W SMC SMC 1 10 F1 OMF125 7A 3404 0019 11 FUSE7 1 11 IC1 ISO2H823V2 ISO2H823V2 PG VQFN 70 2 1 12 JP1 JP2 JP3 Connector 1x3 2 54mm PINHD 1X03_2 54 SL 11 112 36 S 1X03 S 3 13 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LED_GREEN LED SMD GREEN 3 3V 20mA CHIP LED0805 8 14 LD8 LED_RED LED_RED CHIP LED0805 1 15 R1 R2 R3 R4 R5 1k Ohm 1...

Page 27: ...rporated VXWORKS WIND RIVER of WIND RIVER SYSTEMS INC ZETEX of Diodes Zetex Limited Trademarks Update 2014 07 17 www infineon com Edition 2015 02 11 Published by Infineon Technologies AG 81726 Munich Germany 2014 Infineon Technologies AG All Rights Reserved Do you have a question about any aspect of this document Email erratum infineon com Document reference ANEVAL_201412_PL21_006 Legal Disclaimer...

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