Data Sheet
129
Rev. 1.00
2017-07-31
TLE9262BQXV33
Serial Peripheral Interface
16.4
SPI Bit Mapping
The following figures show the mapping of the registers and the SPI bits of the respective registers.
The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only
read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen
with a new read / write command.
The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if
possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to 1. The
registers
WK_LVL_STAT
, and
FAM_PROD_STAT
are an exception as they show the actual voltage level at the
respective WK pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is
recommended for proper diagnosis to clear respective status bits for wake events or failure. However, in
general it is possible to enable drivers without clearing the respective failure flags.
When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:
• The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode
• When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are
not cleared. FOx will stay activated if it was triggered before.
• When changing to SBC Stop Mode, the CAN and LIN control bits will not be modified.
• When changing to SBC Sleep Mode, the CAN and LIN control bits will be modified if they were not OFF or
wake capable before.
• HSx, VCC2 and VCC3 will stay on when going to Sleep-/Stop Mode (configuration can only be done in
Normal Mode). Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up
is issued
• The configuration bits for HSx and VCC2 in stand-alone configuration are cleared in SBC Restart Mode. FOx
will stay activated if it was triggered before. Depending on the respective configuration, CAN/LIN
transceivers will be either OFF, woken or still wake capable.
Note:
The detailed behavior of the respective SPI bits and control functions is described in
Chapter 16.5
,
Chapter 16.6
.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC
will modify respective control bits.
