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The synthesizer features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during
acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as
the frequency difference is near zero. CSP allows significantly faster lock times as shown in
. The
use of the CSP feature is enabled with pfds_rstb (
<15>). The CSP feature may be optimized for a
given set of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting
pfds_sat_deltaN (
<3:0>).
Figure 7. Cycle Slip Prevention (CSP)
6.2 PFD Jitter & Lock Detect Background
In normal phase locked operation, the divided VCO signal arrives at the phase detector in phase with the
divided crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase
of the VCO signal and the reference signal vary in time due to the phase noise of the crystal and VCO
oscillators, the loop bandwidth used and the presence of fractional modulation or not. The total integrated
noise on the VCO path normally dominates the variations in the two arrival times at the phase detector if
fractional modulation is turned off.
If we wish to detect if the VCO is in lock or not, we need to distinguish between normal phase jitter when in
lock and phase jitter when not in lock.
First, we need to understand what the jitter of the synthesizer is, measured at the phase detector in integer
or fractional modes.
The standard deviation of the arrival time of the VCO signal, or the jitter, in integer mode may be estimated
with a simple approximation if we assume that the locked VCO has a constant phase noise, Ф
2
(f
o
), at offsets
less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. The simple locked
VCO phase noise approximation is shown on the left of
Figure 8. Graphical Representation of Locked VCO Phase Noise in the Frequency & Time Domains
