User Manual | PE11S100X Series Synthesizer
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x1x = disable GPO2 pad driver 1xx = disable
GPO3 pad driver
7.30 Reg 1Ch Phase Detector CSP Register
Bit
Type
Name
Default
Description
3:0
R/W
pfds_sat_deltaN
0
0= Cycle Slip Prevention (CSP) disabled
4-bit value to advance or retard phase detector
in VCO cycles if it reaches 2pi, i.e. cycle slip
prevention. 1st bit is polarity, enabled by rstb
4
R/W
pfds_rstb_force
0
CSP PFD Flip-flops RSTB:
1 - controlled by the pfds_rstb bit: 0 - auto-
controlled by the CSP logic
Forces the PFD into reset, which tristates
charge pump, freezes charge on the loop filter,
and hence opens the loop
5
R/W
pfds_rstb
1
CSP PFD FF rstb
1 - Enables the Cycle Slip Prevention (CSP)
feature of the PFD
7.31 Reg 1Dh VCO Tune Port Control Register
Bit
Type
Name
Default
Description
0
R/W
voltage_force
1
Selects the source of control of the timing of the
mid-rail voltage,
voltage_force=0 selects Autotune state machine
voltage_force=1 selects voltage_enable from
SPI Used for mid-rail control of VCO during
autotuning
1
R/W
voltage_enable
0
Forces mid-rail voltage on the charge pump
output from the SPI when voltage_force=1 Used
for mid-rail control of VCO during autotuning
7.32 Reg 1Eh Temperature Sensor Register
Bit
Type
Name
Default
Description
0
R/W
tsens_spi_enable
0
Enable the temperature sensor, draws ~2mA
current, must strobe tsens_spi_strobe Reg 00h
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