Intel 2920, Design Handbook

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Page 2: ...THE 2920 ANALOG SIGNAL PROCESSOR DESIGN HANDBOOK AUGUST 1980 ...

Page 3: ...s document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation The following are trademarks of Intel Corporation and may only be used to identify Intel products BXP Intelevision CREDIT Intellec i iSBC ICE iSBX ICS Library Manager im MCS Insite Megachassis Intel Micromap MULTIBUS MULTIMODULE PROMPT Promware RMX UPI Scope and the combination...

Page 4: ... BLOCK FUNCTIONS FOUNDATION OF DESIGN 4 1 Arithmetic Building Blocks 4 1 4 1 1 Elementary Arithmetic 4 1 4 1 2 Multiplication by a Constant 4 1 4 1 3 Multiplication by a Variable 4 3 4 1 4 Division by a Variable 4 5 4 2 Realizing Relaxation Oscillators 4 6 4 2 1 Reset Technique for Relaxation Oscillator 4 6 4 2 2 Overflow Technique for Relaxation Oscillator 4 7 4 3 Voltage Controlled Oscillators V...

Page 5: ...5 17 5 6 8 Other Filter Structures 5 17 6 0 ADVANCED TECHNIQUES 6 1 Time VarIable Filters 6 1 6 2 Noise Generation with the 2920 6 4 6 3 Digitallnput Output 6 4 7 0 APPLICATION EXAMPLES 7 1 Sweeping Local Oscillator 7 1 7 2 Piecewise Linear Logarithmic Amplifier 7 2 7 3 Digital Filter 7 5 7 4 The 2920 as a Spectrum Analyzer 7 7 7 4 1 Description of Spectrum Analyzer 7 7 7 4 2 Block Diagram Descrip...

Page 6: ...Introduction and Terminology 1 ...

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Page 8: ...20 Signal Processor is a single chip microcom puter designed especially to process real time analog signals The 2920 has on board program memory scratchpad memory D A circuitry A D circuitry digital processor and I O circuitry It is more than a single device but is a complete digital sampled data system The architecture and instruction set was developed to perform precise high speed signal process...

Page 9: ...essing Sonar processing Transducer linearization 1 2 Typical 2920 Design Sequence Designing with the 2920 Signal Processor is best thought of in terms of the building block functions it can imple ment and the application models already available as 2920 routines see Chapter 7 The designer should COn sider short 2920 assembly language routines as tools which can be combined to achieve the desired s...

Page 10: ...the 2920 s operations can be tested changed traced or stored on diskette files for later analysis or documentation SimUlator Test Program System Debug Evaluate System Performance Program EPROM Intellec UPP 103 2920 Personality Card DeSign Venllcallon Figure 1 1 2920 Design Sequence Table 1 3 Development System Provides Computer Aided DeSign Contrast Between Discrete Component and 2920 DeSign Metho...

Page 11: ... part count improved reliability 1 4 and the elimination of costly preCiSion components Also eliminated is the production re tuning or tweak ing so often required in analog systems integration The flexibility for rapid design changes in prototypes is a direct result of the 2920 s programmability Alter native designs are readily compared by reprogramming the 2920 s EPROM The re use of standard debu...

Page 12: ...te heavy commitments 1 5 Intel 2920 Signal Processor Methodology Single chip System tweaking eliminated because performance from device to device is identical digital processing is stable predictable and repeatable Digital accuracy is repeatable Eliminated the 2920 restricts degradation of signal quality to the instants at which signal samples are digitized and converted back to analog Restriction...

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Page 14: ...Sampled Data Systems 2 ...

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Page 16: ... held long enough for subsequent pro cessing such as analog to digital conversion 2 1 Analog to Digital Converter A D The held analog voltage is converted to a digital word This digital word then represents the sampled input signal voltage Since the processor must operate on individual digital words it is necessary to characterize the continuous analog input signal by discrete digital words which ...

Page 17: ...verlay excessively aliasing distortion the continuous signal can be represented by discrete samples at that sampling frequency The quality of representation of a continuous signal by the sampled and digitized signal is determined by several factors a sampling rate b sampling pulse width c sampling stability and d digitizing accuracy The cor responding distortion terms are a aliasing noise b signal...

Page 18: ... A TIME overlapped spectral energy cannot be separated from the desired signal and so a distortion is caused called aliasing noise Figure 2 4 shows the effect of sample rate on aliasing noise for a given input signal Note the amount of overlap increases as the sampling frequency is decreased for a fixed input signal bandwidth Similarly for a fixed sampling frequency the overlap could be reduced by...

Page 19: ...ing fre quency Unless it is compensated for this distortion of the input signal will cause loss of information similar to the loss from a lowpass filter with insufficient band width Table 2 1 lists the rolloff in dB as a function of the sample width T and the signal bandwidth B To correct this situation either the reconstruction sampling pulse width should be made narrow relative to one over the s...

Page 20: ... stable then the signal will be sampled at times other than what was expected with an error corresponding to the rate of change of the sampled signal The jitter noise can be estimated by examining a sinusoidal input signal that is sampled with average period T and a peak to peak deviation of the period 2T Figure 2 7 Using sin wti as the value of the sinusoid exactly at the i th sampling instant an...

Page 21: ...oss of information is possible with the proper selection of the input filter and sampling frequency The conversion from a continuous signal to a digital signal requires that signal voltage be divided into a finite number of levels which can be defined using a digital word n bits long An n bit word can describe 2n dif ferent voltage steps Signal variations between these steps will go undetected It ...

Page 22: ...peak signal power Nq is the mean quantization noise M is the number of quantization levels 2n n is the number of bits in the amplitude word The 2920 has a programmable AID conversion of up to 9 bits of resolution giving the device up to 54dB of instantaneous dynamic range based on quantization noise alone For systems where the total dynamic range is 54dB but the instantaneous requirements are with...

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Page 24: ...The 2920 Signal Processor 3 ...

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Page 26: ... ports to the ALU is passed through a scaler barrel shifter The arithmetic section executes commands from EPROM thereby performing digital simulation of analog functions in real time The analog section performs analog to digital AID and digital to analog 01A conversions upon com mands from the EPROM section The analog section includes an input multiplexer 4 inputs an input sample and hold circuit ...

Page 27: ...take place in as little as 400 nanoseconds depending on the clock rate 3 2 3 2 A Closer Look at the Functional Elements 3 2 1 EPROM Section The EPROM section contains 4608 bits of user pro grammable and erasable read only memory In normal operation of the 2920 i e in the RUN mode it is arranged as 192 words of 24 bits each Each word cor responds to one 2920 instruction During programming each 24 b...

Page 28: ...he pins of the 2920 perform different func tions in the PROG mode than they do in the RUN mode These differences are noted in Figure 3 2 Note that for the 2920 pin outs as shown in Figure 3 2 the power supply conventions are different for RUN and PROG mode These conventions allow the pro grammer designer to use popular TTL family products as a basis for design With the exception of the power conne...

Page 29: ...MODE Symbol 00 01 02 03 Function 4 pins carrying EPROM program data for both input and output open drain active low output active high Input VB VB2 VB3 Digital ground In PROGRAM mode dif ferent voltage for RUN mode VS VS2 VS3 5 volts In PROGRAM mode function changes for RUN mode RUN PROG Mode control pin tied to VBB for PROGRAM mode voltage changes for RUN mode INCR Input pulse Increments the nibb...

Page 30: ...the scaler to one input of the ALU as the source operand The B port passes data to the second ALU input and receives the ALU results as the destination operand The constant array consists of 16 pseudo locations in the RAM address field These constants are accessed only from the A port i e only as a source operand 3 5 The least significant four bits of the address are directly translated to the hig...

Page 31: ... too large to fit within a 25 bit field The handling of such large numbers is described in the ALU section below The ALU The Arithmetic Logic Unit calculates a 25 bit result from its A and B operands source and destination based on an operation code from the EPROM The 25 bit result is written back into the B destination memory location at the end of the instruction cycle One condition for overflow...

Page 32: ...uted A I implies execution of the instruction a 0 implies execution of a NOP For conditional sub tract the bit actually used is the carry from the previous result In this case the selected bit of the DAR is set equal to the carry from the current instruction Conditional additions are used to mUltiply one variable by a second as discussed in Chapter 4 The mUltiplier is loaded into the DAR and the m...

Page 33: ...og Control Field ALU Function Bit Tested IF Tested Bit 0 IF Tested Bit 1 ADD 110 DAR n NO OP B O B ADD B A 2k B LDA lll DAR n NO OP B O B LDA O A 2k B SUB 101 PREV cy ADD B A 2k B SUB B A 2k B cy DAR n cy DAR n Note DAR n represents a bit of the DAR as selected by the conditional operand in the analog control field For ADD and LDA the selected bit is tested For SUB the selected bit is altered by b...

Page 34: ...stants of the output sample capacitor charging circuit Input and output sample rates are determined by the frequency of execution of input conversion sequences and output instructions respectively 3 9 The input channel multiplexer consists of four analog switches which directly connect a common external sampling capacitor to the input terminals The size of the sample capacitor affects the time con...

Page 35: ... logic mode an output pin appears as an open drain circuit capable of sinking 2 5mA Thus a CMOS or TTL gate can be driven if a suitable pull up resistor is used A positive voltage reference supply must be provided by the user The range of acceptable voltages is from 1V to 2V and is chosen to suit the application The input and output voltage range is limited to the range VREF The 01A is a mUltiplyi...

Page 36: ... ADK 0 7 Output Channel k 1 1 CND k ADK 0 7 Condo Artih Test DAR bit k b Code Assignment and Mnemonics ADK ADF 1 0 210 00 01 10 11 000 INO OUTO CVTO CNDO 001 INI OUTl CVTl CNDI 010 IN2 OUT2 CVT2 CND2 o 1 1 IN3 OUT3 CVT3 CND3 100 NOP OUT4 CVT4 CND4 1 0 1 EOP OUT5 CVT5 CND5 1 0 CVTS OUT6 CVT6 CND6 1 I CNDS OUT7 CVT7 CND7 Note The DAR bits are designated S 7 6 0 where S is the sign bit 7 the next mos...

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Page 38: ...Building Block Functions 4 Foundation of Design ...

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Page 40: ...e To better appreciate the complexity of a system that can be implemented with a given size program three examples are given in Table 4 3 which are representative of a wide variety of possible applications 4 1 Arithmetic Building Blocks Among the simplest and most essential routines to be used in building more complex functions are multiplica tion and division both by constants and by variables Th...

Page 41: ... 875 1 0 0 5 0 25 0 125 20 2 1 2 2 2 3 or 1 875 2 0 125 21 2 3 The first expression could be easily derived from the binary representation of 1 875 in binary 1 111 However the second expression uses fewer terms which will result in the use of fewer 2920 EPROM words 4 2 RAM Comment Locations 2 9 Bit X 25 Bit 3 25 Bit 9 Bit 2 A Complex Pole or Complex Zero 2 9 Bit Amp Accuracy 16 Bit Freq Ace 2 Same...

Page 42: ... closest to that of E For example if E were 0 65 T would have the value 0 5 Let V V T 4 3 4 Return to step 2 above with the new value of V and recompute the error E If the error E is small enough the value V is used as equivalent to C If not step 3 must be repeated Because V is expressed as a series of sums and differences of powers of two the term T it can be used to generate the desired 2920 cod...

Page 43: ...he product and separate logic to determine the sign A more direct alogrithm is used in the 2920 to avoid the necessity of dealing with the sign bit separately since bit manipulation is comparatively inefficient in the 2920 Number Representation It is convenient to form a representation of a number in two s complement nota tion since this notation is hardware efficient and is used in the 2920 Assum...

Page 44: ...r to divide a variable by another variable uses the conditional subtract The basic alogrithm is intended for division of positive numbers by positive numbers If negative variables are to be used the sign of the quotient may be computed using XOR and the absolute magnitudes of the variables are used The full sequence for a four quadrant divide Y X W The sequence consists of conditionally subtractin...

Page 45: ...a sequence of samples of a sawtooth waveform If a different waveform is desired either filtering or waveform modification is necessary Caution must be exercised when linear filtering is used since the samples of a sawtooth represent samples of a signal that is not band limited Therefore the higher harmonics of the original sawtooth may beat with harmonics of the sampling fre quency to produce spur...

Page 46: ...4 2 2 Overflow Technique for Relaxation Oscillator It is possible to generate a sawtooth waveform using the overflow disable operations described in Table 3 4c In some cases this technique may yield a shorter overall program length The technique involves using the wraparound characteristics of a non overflow cor rected 2 s complement number system that is if you add 1 to the most positive number t...

Page 47: ...requency accuracy In addition overflow saturation may produce undesirable effects on oscillator behavior Each time saturation is entered the oscillator behaves as if a small quantity was added to YO Such a change corresponds to a change in both amplitude and phase The amplitude change may introduce undesired harmonic content and the phase change may result in a change of frequency so that the osci...

Page 48: ...magnitude function Y IX I can be realized with a single 2920 instruction ABS This func tion behaves as an idealized full wave rectifier The add absolute function ABA is useful for combining full wave rectification with input to a filter Half wave rectifiers can be realized using the equation y x Ix I 12 The corresponding 2920 code for this operation is as follows LDA Y X ROl Y X 2 ABA Y X ROl Y XI...

Page 49: ...ape curve as that of Figure ADD T A LOI X A in T 4 3 with a value of L 2a This form generally takes ABS T T ROO ABS X A in T more steps than the overflow saturation method but SUB Y T ROO Y ABS X A ABS X A allows greater freedom in setting parameters The 2920 code might appear as follows where A represents the limiter threshold and T is a location used only for intermediate calculations 4 10 ...

Page 50: ...Summary of 5 Filter Characteristics ...

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Page 52: ...ptotic limit in filter selectivity with a minimum of distortion Realizable filters can approach this selectiv ity by increasing the number of poles or stopband zeros in their transmission function Phase linearity must be maintained either by employing direct linear phase syn thesis techniques or by using phase equalizers to linearize the phase characteristic of the filter It is of interest to stud...

Page 53: ...se filters The poor pulse response is caused by both the high selectivity and the nonlinear phase characteristics of the filters 5 2 Typical applications of this type of filter include signal rejection frequency domain shaping of a spectrum or other amplitude response applications where the phase distortion of the signal is not important e g filtering a fixed tuned linear oscillator 5 2 2 Chebyshe...

Page 54: ...functions can be described such as equal ripple phase parabolic monotonic L etc Their characteristics are combinations of those already described The important aspect of minimum phase filters is the unique relationship between amplitude and phase The transient response is affected by both parameters so that flexibility is limited with respect to simultaneously achieving good selectivity and low di...

Page 55: ...l have the same general characteristics It can be seen that filters optimized for a particular amplitude characteristic have pole locations inside the circle passing through the cutoff frequency similarly 5 4 w 0 laB CHEBYSHEV BUTTERWORTH h EQUAL RIPPLE PHASE T BESSEL ALL ZEROS AT w I f Figure 5 2 Pole Zero Locations Of 4 Pole Lowpass Prototype Filters filters optimized for linear phase properties...

Page 56: ...linearized The step response of a single pole network is illustrated in Figure 5 5 Because the rise time of cas caded filter sections is approximately equal to the 5 5 04 03 BESSEL 1 BUTTERWORTH t 01 dB CHEBYSHEV M OS LINEARPHASE i I 1 02 if i 01 1 J i y 01 L o 10 08 04 12 TIME Lr _ I I 01 dB CHEBYSHEV II i BUTTERWORTH BfSSEL j O S LINEAR PHASE 1 l i o j Y Figure 5 4 Impulse And Step Response Of L...

Page 57: ... expected from the analysis of the rectangular filter whose linear phase and rectangular amplitude response represent the limiting case as the number of poles goes to infinity for phase linearized filters 5 6 20 15 3 BUTTERWORTH 05 dB CHEBYSHEV LINEARIZED __ ____ BUTTERWORTH w4ATTEN 3 LINEARIZED 0 5 CHEBYSHEV LINEAR PHAse TRANSITIONAL BUTT GAUSSIAN TO 6 dB 05 EQUAL RIPPLE PHASE B SSEL GAUSSIAN O L...

Page 58: ...s of the original analog filter Phase equalizers may be designed to linearize the phase characteristic of the transformed digital filter 5 5 2 FIR Digital Filters Finite impulse response filters offer several advantages Some of these advantages are 1 FIR filters can be designed to have exactly linear phase Linear phase filters are important for applications such as speech processing and data trans...

Page 59: ...mpulse response whose values at each sample time are identical to those we would expect from Fl This impulse response may be achieved by building a network of the structures shown in Figure 5 7 and 5 8 and summing their outputs This procedure defines a type of transform from the continuous domain to the sampled domain that is the sampled domain structure implements an impulse response equivalent t...

Page 60: ... In polar coordinates this z plane location is eaT bT The equa tions for the filter coefficients are shown below Second order sections for a continuous pole pair a jb in the s plane B 2e at cos bT B2 e 2aT for a continuous zero pair at a jb A 2Aoe aT cos bT A2 Aoe 2aT First order section for a real pole at a B e aT for a real zero at a A Aoe aT This transform is not guaranteed equivalence in eithe...

Page 61: ...linear transform are shown below The equations for the Bilinear Transform are where T is the sampling interval z 2IT S 2 T S That is given a polynomial expression in s for the transfer characteristic of a continuous filter a cor responding digital filter may be found by substituting 2 l_Z I T l Z I for each occurrence of s and then converting the resulting expression to a ration to two polynomials...

Page 62: ...ue of YO from the previous pass To complete the filter realization it is sufficient to complete the calculations of the new value of YO from the current values of input Y1 and Y2 and then compute the output from YO Yl and Y2 The new value of YO involves multiplication of Yl and Y2 by the constants Bl and B2 The instruction set of the 2920 permits implementing these multiplications by constants as ...

Page 63: ... best values for Band G that are consistent with meeting of design goals and also are easily realized in 2920 code It is the function of the 2920 support soft ware to aid in optimizing 2920 code subject to design bounds The example given below is intended to illus trate the procedures involved Design Example No 1 For a sample interval of 76 8 Ilsec realize a single pole filter with a time constant...

Page 64: ...Pole Pair 5 13 Figure 5 13 shows the frequency response of this type of stage The choice of parameter values determine both the frequency at which the gain peaks and the Q or sharpness of the peak 50 z FREQUENCY I 2rr LC Figure 5 13 Gain Of Complex Conjugate Pole Pair Section The FORTRAN equations for a complex conjugate pole pair section are as follows Y2 YI YI YO YO BI YI B2 Y2 G X Once the coef...

Page 65: ...O X YO X ROO ROO LOI R02 R06 ROO R07 R09 R03 RIO Y2 YI YI YO YO BI YI YO BI YI B2 Y2 YO BI YI B2 Y2 G X 5 14 The comments show how the values are built up from sequences of 2920 instructions by alternating ADD and SUB commands to maintain the smallest total and thus minimize the possibility of overflow 5 6 3 Realizing Zeros in Basic Filter Sections The building blocks described above realize only ...

Page 66: ...amic 5 15 range of the amplifiers However an additional con sideration may be important in 2920 realizations of second order sections As coefficient products are developed by series of additions and subtractions intermediate values may be larger than those finally obtained In general it is necessary to provide sufficient margins when scaling input variables to ensure that overflow saturation does ...

Page 67: ...y closely the values 2 and 1 respectively By realizing the filter as shown in Figure 5 11 the small terms BI 2 and B2 1 are isolated from the large terms and scaled upwards by some power of two The equivalent multiplications may then be done using single precision which is converted back to extended precision by a 2 n scaling Extended precision arithmetic may be executed using masks derived from t...

Page 68: ...ling the inputs at a higher than normal rate and performing some of the anti aliasing using a 5 17 digital filter stage operating at this higher rate Subse quent processing of the data is performed at the nominal rate of the 2920 One means for achieving the higher sample rate is to use two copies each of the sampling routine and the anti alias digital filter section Figure 5 18 shows the impact on...

Page 69: ... beyond fs BW 1 EXTERNAL ANTI ALlAS FILTER L INTERNAL DIGITAL FILTER b Spectrum using double rate sampling 215 External filter passes BW stops beyond 2fs BW internal digital filter performs rest of anti alias function Figure 5 18 Effects of Double Rate Input Sampling 1 8 Figure 5 19a Cascade Structure for Complex Filter Directly Derived from Matched Z or Bilinear Transform 5 18 ...

Page 70: ...SUMMARY OF FILTER CHARACTERISTICS 0 0 0S Figure 5 19b Parallel Structure for Complex Filters May Result from Impulse Invariant Transform 5 19 ...

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Page 72: ...Advanced Techniques 6 ...

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Page 74: ...ximations may be used B2 e 2n b fsl Bl 2e nb fs cos 2nfo fs where fs is the sampling frequency fo the filter center frequency and b is the filter bandwidth Note that the relationship between center frequency and controlling parameter B2 is nonlinear following a cosine curve In some cases a nonlinear transformation may be used to compensate for this nonlinearity see section 4 6 on nonlinear transfo...

Page 75: ...ilter can be found from For the coefficient values given the maximum gain is 21 9 when c 1 0 Note that the gain varies with the value of c reaching a minimum when c O O of 17 9 corresponding to a 1 76 dB gain variation over the setting range If such a varia tion is unacceptable c may be used to weight the input X to compensate For example if the weighting of X is of the form X 2c ll 1256 overflow ...

Page 76: ...CND6 CND5 CND4 CND3 CND2 CNDI CNDO add 0 75 YI to YO to complete BI YI ADD YO YI RI ADD YO Yl R2 1I16 Y2 in YO 15 16 Y2 in YO add in input to filter scaled to prevent overflow ADD YO YI R5 filter range is 569 to 1493 Hz center frequency resolution is 6 Hz at 569 3 Hz at 1493 Table 6 1b Gain Compensation in place of the last code line of table 6 la which added in the input scaled to avoid overflow ...

Page 77: ...hat is the natural format of the data bit serial or parallel for example What controls the transfer Is the 2920 the master or the slave in the 110 process Is the transfer synchronous or non synchronous with the 2920 program execution What resources are available on the 2920 for digital 110 after the main function has been accomplished how many SIGIN or SIGOUT pins are free How much program space i...

Page 78: ...per program pass RST can be a non synchronous control input when gated with CCLK Each complete 110 operation may consist of four dif ferent operations a control sequence a data assembly or put away sequence a data transfer sequence and a clocking or activation sequence Specific examples are given using the different inputs and outputs on the 2920 The examples are not exhaustive but they show some ...

Page 79: ...in Multiple bytes per program pass can be out putted with the 2920 as master and one control signal see Figure 6 5 Table 6 4 shows the instruction sequence Table 6 4 Digital Output Serial Instruction Sequence Instruction sequence LDA DAR KP7 OUTO LDA DAR DATA 3 LDA R KPO 0 LDA R KP4 1 NOP 2 LDA R R LDA R KPO LDA R KP4 LDA DAR KPO LDA R R OUTO Summary Analog instructions Digital instructions Input ...

Page 80: ...ll assert OF even if the condition is not met Figure 6 6 Overflows may occur during other portions of the pro gram since there will be no clocking of the shift register OVERFLOW DURING INSTRUCTION 2 Input Parallel For synchronous parallel input of one byte per program pass with the 2920 as master Table 6 5 shows the instruction sequence With a 10 MHz clock a transfer rate of 37 5 K Byte sec is obt...

Page 81: ...y locations Overflow L2 L2 Select higher order four bits Load DAR FS 4 Input Bit 3 Convert Bit 3 Repeat through Bit 0 DAR contains four higher order bits MSB s Left shift DAR four bits and store in 0 Select lower order four bits Load DAR FS 4 DAR contains four lower order bits Combine high and low order bits SA 2B 8C 9 4 I I Not affected A equals the number of IN instructions and C equals the CVT ...

Page 82: ...s parallel loads The transfer is synchronous with the 2920 as master and multiple bytes can transfer per program pass see Figure 6 8 Table 6 6 shows the instruction sequence T LOAD 1CLOCK INHIBIT DATATAKEN LOAD DATA SERIAL 1 5kQ 07 OUT 74165 DATA IN DO ICLOCK With a 10 MHz clock a transfer rate of 30K Bytes sec is obtained for the instruction sequence or up to twice that amount per full program pa...

Page 83: ...ter INO Input D6 CVT2 LDA R KP7 Ll Repeat through D4 CVTO LDA R KP7 Ll SUB DAR KP2 DAR contains 07 04 LDA 0 OAR L2 Left shift OAR two bits into D LOA OAR KP2 Repeat for 03 00 INO CVT3 LDA R KP7 Ll CVTO SUB DAR KP2 DAR contains 03 00 XOR DAR D L2 OAR contains 00 07 LOA D DAR Load 07 00 into D LOA OAR KP7 OUTl Disable clock Summary Analog instructions 8A 3B 8C Oigital instructions 19 Input pins I Ou...

Page 84: ... the IOF 2920 1 X1y21 I EOP 1 EXT elK ExTCLi S 6K number which is converted back in the receiving 2920 This method is limited to about four bits per transfer because the effective gain between an output and an input is approximately 0 9 Generally fewer instructions and or greater speed result if the overflow is used for outputting and one bit conversion made on input The input analog sample time i...

Page 85: ...d bit counter Test bit counter Full byte taken Store byte Clear shift register Test BYTE Output BYTE TAKEN Clear BYTE TAKEN Clear Data taken This sequence loads a serially input byte 8 bits into location DATA If multiple bytes are to be input then an additional counter shift register can be added at the end to sequentially update each of four data bytes DATAO 3 LOA DAR BYTE New byte available LOA ...

Page 86: ...Application Examples 7 ...

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Page 88: ...ncy of the yeO its frequency range and the rate of change of frequency It does so by pro ducing a sawtooth wave whose slope determines the rate of change whose voltage excursion is proportional to the frequency range and whose offset represents the minimum of that range The sawtooth wave is simple to generate continuous decrementing of a register by a fixed value produces a linear negative slope W...

Page 89: ...sinusoid Investigation of the Fourier Transforms of various sym metric waveforms reveals that a trapezoidal waveform can be adjusted so that even harmonics are eliminated and the first odd harmonic is the fifth This adjustment is done by selecting the top of the trapezoid to be 2 3 of the peak of a corresponding triangle wave The flow diagram to accomplish this transformation is shown in Figure 7 ...

Page 90: ...RAMSIZE ROMSIZE 18 SeT SWEEP RATE FOR SLo 4HZ SWEEP RATE GENERATOR IS HI RESET HI IF 0 H2 IS SCALED SWEEP WAVE FORM WHICH DRIVES VCO RESULTING IN SLO MAX FREGUENCY OF 13KHZ VOLTAGE CONTROLLED OSCILLATOR RESET VCO IF 0 WAVESHAPING WILL BE DONE IN RAM LOCAl ION OSC CENTER SAWTOOTH ABOUT ZERO DOUBLE AND TAKE ABSOLUTE VALUE CENTER TR IANCLE WAVE ABOUT ZERO MULTIPLY BY THREE WAVEFORM IS CLIPPED TO BECO...

Page 91: ...ds to inputs less than 1132V However all input signals regardless of amplitude are processed by the equation for this section initially The original signal is then placed in the DAR All the following operations are conditional and are performed only if the tested bit of the DAR is a one Otherwise a NOP is performed Each bit of the DAR is tested starting with bit 3 and progressing to bit 7 When a o...

Page 92: ...d nor malized to 1 rad sec bandwidth The normalized and denormalized values are listed in Table 7 1 for the selected filter Table 7 1 Pole Zero Locations Singularity Normalized Denormalized 1 rps 1 KHz Simple Pole 00 0 83124 00 5222 rps Wo 0 Complex Pole 01 0 31128 01 1955 8 rps Pair WI 1 09399 WI 6873 7 rps Complex Zero 02 0 02 0 rps Pair W2 2 2701 W2 14263 rps The corresponding gain vs frequency...

Page 93: ... YOO YOI R4 4 40009C ADD YOO YO I R5 5 40003B SUB YOO YOI RIO POLE 2 3 6 4200EF LOA Y12 YII 7 4608EF LOA YII YIO 8 44085E LOA Y1 O YOO R3 9 4600BC ADD YIO Yl1 R6 10 4600FD ADD YIO YII RO II 46003C ADD YIO Yl1 R2 12 4400lA SUB YIO Y12 RI 13 44005A SUB YIO Y12 R3 14 44009A SUB YIO Y12 R5 15 4400BA SUB YIO Y12 R6 ZERO I 2 16 4208ED ADD SIGOUT YIO 17 42002A SUB SIGOUT YII R2 18 42008A SUB SIGOUT YII R...

Page 94: ...og block diagram of the application is complete it is relatively straightforward to implement each subsystem as a block of code in the 2920 signal pro cessor The following section describes the block diagram of the spectrum analyzer and discusses design considerations Implementation of the spectrum analyzer is discussed in terms of the actual design pro cess using the signal processor 7 4 1 Descri...

Page 95: ...e BPF and the signal energy is extracted When the SLO is at 1 3 KHz the BPF is looking at the high band 3 2 KHz As the INPUT I SIGNAL T MIXER SLO frequency increases at a SLO frequency of 4 3 KHz the BPF sees the signal energy at 200 Hz 4 5 KHz minus 4 3 KHz The block diagram shows that the BPF output is then passed through a full wave rectifier FWR and lowpass filter to extract the envelope from ...

Page 96: ... of the bandpass filter is determined by the input lowpass filter bandwidth and rolloff Figure 7 12a and the aliased spectrum of the lower sideband resulting when the SLO is at 4 3 KHz Figure 7 12c The BPF must have enough rolloff to 7 9 eliminate both the baseband and aliased out of band signal components that are present Analysis shows that a 3 pole Bessel filter will suffice if the input LPF is...

Page 97: ...as significant frequency components above about 7 KHz If a controlled signal is to be processed by the spectrum analyzer such as sine waves or narrow band signals no anti aliasing filter is needed 7 10 7 4 4 Complete Spectrum Analyzer Assembly Listing The spectrum analyzer program listed in Figure 7 13 was coded in a structure form with each functional block coded separately and the blocks arrange...

Page 98: ...sawtooth is set to zero at the beginning of each sweep so that the veo output can be more easily observed with an oscilloscope Once both the veo waveform and the input signal have been obtained they are multiplied together using the four quadrant mUltiply algorithm The signal from the multiplier mixer is then passed to the 6 pole bandpass filter Portions of the output sequences for the veo and lin...

Page 99: ... TEMP R06 NOP 26 21 450000 ADD IFI0 TEMP R09 CVT4 27 22 440020 ADD IF10 TEMP RI0 NOP 28 23 44006B SUB IFI0 TEMP R12 NOP 29 30 POLE 3 31 24 3308EF LDA TEMP IF31 ROO CVT3 32 25 4COOFF LOA IF31 IF30 ROO NOP 33 26 40100F LOA IF30 TEMP R09 NOP 34 27 21100A SUB IF30 TEl lP RO CVT2 35 28 40104A SUB IF30 TEMP R03 NOP 36 29 48106C ADD IF30 IF30 R04 NOP 37 30 13184C ADD IF30 IF31 R03 CVTl 38 31 42188A SUB I...

Page 100: ...9 86CABC ADD 52 KP3 R06 OUTO 76 60 84CAID ADD 52 KPl R09 OUTO 77 61 8668ED ADD F2 52 ROO aUTO iADD OFFSET 78 79 80 i vca 81 82 83 62 8000EF aUTO 84 63 8270EB SUB aSC1 F2 ROO OUTO 85 64 4864EF LDA DAR aSC1 ROO 86 65 7A58ED ADD OSC1 M ROO CNDS 87 66 4870FF LDA OSC OSCI ROO 88 67 4A581A SUB OSC M ROl 89 68 4878D7 ABS OSC OSC LOl 90 69 4A581A SUB OSC M ROl 91 70 4064EF LDA DAR Fl ROO 92 71 70D2EF LDA ...

Page 101: ...401AE LOA BP30 TEMP R06 OUT2 131 97 4401EB SUB BP30 TEMP ROO 132 98 42CCEF LOA DAR YO ROO I LINEAR OUTPUT TO DAR 133 99 4681CA SUB BP30 BP30 R07 NOP 134 100 4489EB SUB BP30 BP31 ROO NOP 135 101 44894A SUB BP30 BP31 R03 NOP 136 102 44898A SUB BP30 BP31 ROS NOP 137 103 4489CC ADD BP30 BP31 R07 NOP 138 139 iPOLE 5 140 104 4880EF LOA TEMP BPS ROO NOP 141 105 C899EF LOA BP51 BPSO ROO OUT4 142 106 C0119...

Page 102: ...85 137 42CCEF LDA DAR YO ROO 186 138 B799AF LOA LOUT YO L02 CND3 SECTION 5 187 139 B793ED ADD LOUT KP2 ROO CND3 188 140 BD9B8C ADD LOUT KP5 R05 CND3 189 141 C799CF LOA LOUT YO LOl CND4 SECTION 4 190 142 C79BED ADD LOUT KP3 ROO CND4 191 143 C7936C ADD LOUT KP2 R04 CND4 192 144 D799EF LOA LOUT YO ROO CND5 SECTION 3 193 145 DD93ED ADD LOUT KP4 ROO CND5 194 146 D7936C ADD LOUT KP2 R04 CND5 195 147 E79...

Page 103: ...OF8F1FEFAFAFOFOF1FEFBBE 18022800FAFOFOF1F8FCFAFOFOF1FCFAFAFOF8F8FEFFFAF2F8F1FFFF94 18024000FAF4FOF1FAFEF4F4FOF1FEFBF4F2FCFCFEFFF4F6F8F1FCFA79 18025800F4F4F8F9FEFBF4F4F8F9F4FAF4F4F8F9F8FAF4F4F8F9FCFC59 18027000F4F8F8FOFEFFFCF8F9F9FEFFFCFOF1F1F9FEFCFOF1F1F3FD3F 18028800FCFOF1F1FFFBFCF8F9F9FFFCFCF8F9F1FFFBF4F8F9F1F5FA18 1802AOOOF4FAFCF4FEFFF4F8F9F1FBFCF4F8F9F1FIFBF4FAF2F1FAFC15 1802B800F4F4F8F1F6FCF4...

Page 104: ...Design Considerations 8 ...

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Page 106: ... operation is the master clock Timing requirements include a duty cycle of 50 5 0 0 or better and a rise or fall time of less than 5 nanoseconds Voltage high levels should be greater than 1 volt and low levels less than 4 volts Rise and fall times should be measured between 1 and 4 volts TTL with Vcc 5V If CCLK is jittery or erratic the prob lem is usually in the master clock 8 1 INPUT 010 5 VOLTS...

Page 107: ... following amplifier It is important for proper A D DIA conversion that VREF remain constant and provide a noise free voltage source To ensure a low noise DC output a shunt capacitor is located at the input of the op amp Also a bypass 8 2 capacitor is connected between VREF and GRDA The noise at the VREF pin should not exceed 4 mV If it exceeds 4 mV the noise will couple into the A D DIA converter...

Page 108: ...ation As an output it signifies EOP instruction present open drain active low Symbol OF VSP M1 M2 Function Indicates an overflow in the current ALU operation open drain active low EPROM powerPrnOvoltsforRUN mode Different voltage in program mode Two pins which specify the output mode of the SIGOUT pins see Table 4 SIGOUT 3 SIGOUT 2 SIGOUT 4 SIGOUT 1 SIGOUT 5 SIGOUT 0 GRDA Ml SIGOUT 6 M2 SIGOUT 7 V...

Page 109: ...Vee DESIGN CONSIDERATIONS Vee 5V VBB 5V SIGOUT 7 SIGOUT 5 SIGOUT 3 SIGOUT 6 SIGOUT 4 SIGIN 3 SIGIN 0 SIGOUT 2 SIGOUT 0 SIGOUT 1 5V 5V Figure 8 3 Schematic Diagram 2920 Application Breadboard 8 4 ...

Page 110: ...or Note 1 8 5 C1 1 0 J LF Ceramic Capacitor C2 1J LF Ceramic Capacitor C3 500 pF Ceramic Capacitor C4 1J LF Ceramic Capacitor C5 100 J LF Tantalum Capacitor C6 1 J LF Ceramic Capacitor C7 1 J LF Ceramic Capacitor C8 100 J LF Tantalum Capacitor C9 1 J LF Ceramic Capacitor CIO 1 J LF Ceramic Capacitor CI1 1 J LF Ceramic Capacitor Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 ...

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Page 112: ...2920 Support Tools 9 ...

Page 113: ... E w I en en I z w E a o J W W c a o en en w o a a ...

Page 114: ... are encountered 2 Location Counter Management keeping track of locations available for instructions and assigning locations for each instruction assembled 9 1 3 Instruction Assembly translating mnemonic opcodes and operands into their machine language equivalents 4 Control and Directive Processing noting and executing all controls e g assembly listing and object output control and directives such...

Page 115: ...sing This controlled break in execution is called a BREAKPOINT The ability to review the values of key variables or the steps of the simulation as they occurred prior to the breakpoint is called tracing i e collecting and displaying TRACE information Similarly it is useful to be able to display and alter data or instructions in any Random Access Memory RAM or Read Only Memory simulated EPROM locat...

Page 116: ... desired 9 3 Another session may be started immediately resetting all parameters to their initial values by a few simple commands or return to ISIS II can be done using the EXIT command The Simulator also contains detailed HELP messages for commands and syntax A sample 2920 simulator session is shown in Figure 9 2 5112 20 L1ST SAW LOC I SA OUTPUT FlU THIS SESSION IN LOC FILE LOAD SAW NEX I LOAO UI...

Page 117: ... 9 4 usually but not always linear The theory relating con tinuous analog filters to sampled digital filters appears in Chapter 5 Filters are usually designed to achieve certain gain anc l phase characteristics which can be viewed as resulting from the location of the filter s poles and zeros The desired output amplitude and phase can be approached in an interactive design session by placing poles...

Page 118: ...e Parameter files saved from an interrupted design session can then be included at a later date to resume that design session with all relevant variables restored to their condition at the time the session was interrupted Compound Commands SPAS20 contains macro and compound command facilities which enable multi ple and conditional execution of command sequences including substitution of varying pa...

Page 119: ...SE OYER THE OLD i 1 1 I 0 12 I 1 i lO ll l 2 3 4 3 H J 41 4 6 I H2 100 150 200 300 400 500 700 1000 1400 2000 3000 c F LUS SICHS INDICATE OLD CURVE HOTE THAT THE DICITH FILTER RESPOHSE BEGINS TO IHCREASE ACAIN AT HAlF THE SAIIPlE RIITE 10 NZ THE PHASE CHARACTHISTICS OF THIS FILTER CAM BE EXA IHED StolLE Fl PI CR PH PHASE PH S 3 2 H 2 4 2 24 I I 5 135 I 05 o 75 a 5 o 5 I ESTABLISHES RANCE OF INTERE...

Page 120: ...OUTO_PI t 12500000_0UTO_PI 0 21484175_0UTI_PI 0 50000000 0UTZ PI SUB OUTO_PI OUTLPI ROB OllTO_PI 1 12500000_0UTO_PI 0 214B4175_0UTI_PI 0 50B0625 0UT2_PI ADD OUTO_PI OUTZ_PI RlI OUTO_PI I IZ50000000UTO_PI 0 2148437 _OUTI_PI 0 03417HoOUTZ_PI SUB OUTO_Pl OUT2_PI RO OUTO_PI I IZ500000_0UTO_ I O 214B4175 0UTLPI 0 5051710 OUTZ_PI ADO OUTO_Pl IHO_PI ROO OUTO_PI I 12500000 0UTO_ 1 0 214B4375 0UTI_PI 0 O 1...

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Page 122: ...Appendix Evaluating 2920 Applications ...

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Page 124: ...led analYSis would have to be made and a prototype program actually written to determine applicability of the 2920 In many cases where an entire application as specified by the customer cannot be done with one 2920 part of it could be done reducing costs and component count sufficiently to give the 2920 an advantage over another solution EVALUATING A POSSIBLE 2920 APPLICATION Is 2920 dynamic range...

Page 125: ...threshold detection with the 2920 lor example there will be a 54dB dynamic range max However an application requires a minimum SNRa for processing then the total signal range will be 54dB SNRa where SNRa Is the minimum signal to quantization noise ratio that Is acceptable QUANTIZATION NOISE M _______ _ _ _ _ _ __ OUTPUT VOLTAGE Jo 2N l N BITS Jo 6N DB IMAX I I I I 1 ERROR VOLTAGE I t t I t t I I I...

Page 126: ... the sample rate and hence the signal bandwidth for a given 2920 application Because of the restriction on the placement of the EOP instruction program lengths will always be a multiple of 4 A typical program length of from 80 to 192 instructions will yield a bandwidth in the range of DC 10kHz The shorter a 2920 program is the higher the bandwidth which can be handled The minimum length for a 2920...

Page 127: ... 1 Sample Period Subtotal Overhead 510 TOTAL 34 2444 812 23 814 27 FUNCTIONAL EQUIVALENTS FOR 2920 IMPLEMENTATION Analog Function 2920 Equivalent Function Comment Amplitude Modulator Multiplier Frequency Modulator Voltage Controlled Waveform Generator Amplllude Detector Absolute Value LPF Frequency Detector Delay LIne Discriminator Phase Detector Multiplier and LPF Unit Delay Transfer Data From On...

Page 128: ...ed Input Output Opera Opera Instruc Accuracy lions lions tlons 9 Bits 10MHz 33 15 54dB 5MHz 22 8 I MHz 20 2 6 Bits IOMHz 24 15 36dB 5MHz 16 8 IMHz 14 2 I Bit IOMHz 6 15 Serial 5MHz 4 8 Digital 110 IMHz 3 2 TOTAL WORKSHEET 32920 FINAL WORKSHEET 2920 APP 111 APP 112 APP 3 APP 4 Dynamic Range 54dB Bandwidth y Sample Rate Instructions 1 0 192 Digital 192 1 RAM Locations 40 II Inputs 4 1 Outputs 8 A 5 ...

Page 129: ...R I BPF I LIMITER L _ _ _ TRANSMITTER DIGITAL FSK IN OUT This is not sufficient becuase it does not identify 2920 building block functions Further questions yielded the following diagram and block delinition A 6 The modem FSK modulator will convert a serial digital input into a continuous analog FSK output which can be transmitted over a telephone line Since four frequencies will be used DC off 90...

Page 130: ...put signal which will contain the fre quency information and provide a constant amplitude regard less of input signal level This limiting is a nonlinear process and generates harmonics which will be reflected around the sampling frequency in a sampled data system 80 in the 2920 the signal level normalization is accomplished with an auto matic level control which will not add additional harmonic co...

Page 131: ...lex Pole Pair 16 Bit 25 Bit 9 BII 25 Bit 12 18 26 10 Complex Zero Pa When hnked with pole separate 2 5 10 7 1 Full Quadrant S cllon Pole Zero Pllr 1222 34 Singl Real Pol 26 12 lngl Real Zero When hnked with pole separate 2 2 Cascaded Qu dradlcs 2 Pole Zero Pairs J Pole 2 Zero Filler 1 Real and 1 Complex Pole Sawtooth Wave Generator 37 Tnangle Wave Generalor SlneW vaGenerator SLO Sweeping 1CO volta...

Page 132: ...ODEM RAM DIGITAL INSTRUCTIONS 1 0 INSTRUCTIONS 40 152 75 This corresponds to a sample rate of 10MHz 1 F s 4 152 16 4kHz So the 13 6kHz sample rate desire can be achieved THIS APPLICATION CAN BE DONE WITH ONE 2920 APPENDIX A 9 Since some RAM locations used by one functional block can usually be reused by another this estimate for the number of RAM locations needed is probably high Since I O and dig...

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Page 134: ...cs Jan 31 1980 Pg 102 8 An NMOS Microprocessor for Analog Signal Processing M Townsend M E Hoff R Holm IEEE Journal ofSolid State Circuits Feb 1980 9 A Single Chip NMOS Signal Processor M Townsend M E Hoff IEEE ICASSP 1980 DSP 5 7 10 An Analog Microcomputer for Signal Processing M Townsend M E Hoff National Telecommunications Conference 11 28 79 Session 25 11 An Analog Microcomputer M E Hoff M Tow...

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Page 140: ...33 EMCCorp 381 Elliot Street Newton 02164 Tel 617 244 4740 TWX 922531 MICHIGAN Intel Corp 26500 Nonhwestern Hwy Suite 401 Southfield 48075 Tel 313 353 92O TWX 81 244 4915 MINNESOTA Intel Corp 7401 Metro Blvd Suite 355 Edina 55435 Tel 612 835 8722 TWX 91 576 2867 MISSOURI Intel Corp 502 Eanh City Plaza Suite 121 Eanh City 63045 Tel 314 291 1990 Technical Representatives Inc 502 Eanh City Plaza SUit...

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Page 145: ...Metro Blvd Suite 355 Edina 55435 Tel 612 835 6722 TWX 910 576 2867 MISSOURI Intel Corp 502 Earth City Plaza Suite 121 Earth City 63045 Tel 314 291 1990 NEW JERSEY Intel Corp 2450 Lemoine Avenue Ft Lee 07024 Tel 201 947 6267 TWX 710 991 8593 OHIO Intel Corp Chagrin Brainard Bldg 11210 28001 Chagrin Blvd Cleveland 44122 Tel 216 464 2736 TWX 810 427 9298 Intel Corp 6500 Poe Avenue Dayton 45414 Tel 51...

Page 146: ...ARD FIRST CLASS PERMIT NO 621 SANTA CLARA CA Pos tage will be paid by Addressee Intel Corporation Attn Literature Department 3065 Bowers Avenue Santa Clara California 95051 III NO POSTAGE NECESSARY IF MAILED IN THE u S ...

Page 147: ...s Intel s major technical catalogs and manuals I have an immediate requirement Please contact me My application is ___________________ I d like to purchase the following catalogs o MCS 86 Family User s Manual 7 50 o 1980 Component Data Catalog 7 50 o 1980 Systems Data Catalog 5 00 o Peripheral Design Handbook 7 50 Prices are subject to change without notice To order send check money order or use y...

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