Datasheet, Volume 1
73
Thermal Management
Note:
When temperature is retrieved by processor MSR, it is the instantaneous temperature
of the given core. When temperature is retrieved using PECI, it is the average of the
highest DTS temperature in the package over a 256 ms time window. Intel
recommends using the PECI reported temperature for platform thermal control that
benefits from averaging, such as fan speed control. The average DTS temperature may
not be a good indicator of package Adaptive Thermal Monitor activation or rapid
increases in temperature that triggers the Out of Specification status bit within the
PACKAGE_THERM_STATUS MSR 01B1h and IA32_THERM_STATUS MSR 19Ch.
Code execution is halted in C1–C7. Therefore, temperature cannot be read using the
processor MSR without bringing a core back into C0. However, temperature can still be
monitored through PECI in lower C-states except for C7.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (T
j,max
), regardless of
TCC activation offset. It is the responsibility of software to convert the relative
temperature to an absolute temperature. The absolute reference temperature is
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the
DTS is an implied negative integer indicating the relative offset from T
j,max
. The DTS
does not report temperatures greater than T
j,max
.
The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor
trigger point. When a package DTS indicates that it has reached the TCC activation (a
reading of 0h, except when the TCC activation offset is changed), the TCC will activate
and indicate a Adaptive Thermal Monitor event. A TCC activation will lower both IA core
and graphics core frequency, voltage or both.
Changes to the temperature can be detected using two programmable thresholds
located in the processor thermal MSRs. These thresholds have the capability of
generating interrupts using the core's local APIC. Refer to the
Intel
®
64 and IA-32
Architectures Software Developer's Manuals
for specific register and programming
details.
5.4.1.2.1
Digital Thermal Sensor Accuracy (Taccuracy)
The error associated with DTS measurement will not exceed ±5 °C at Tj,max. The DTS
measurement within the entire operating range will meet a ±5 °C accuracy.
5.4.1.3
PROCHOT# Signal
PROCHOT# (processor hot) is asserted when the processor core temperature has
reached its maximum operating temperature (T
j,max
for a timing
diagram of the PROCHOT# signal assertion relative to the Adaptive Thermal Response.
Only a single PROCHOT# pin exists at a package level. When any core arrives at the
TCC activation point, the PROCHOT# signal will be asserted. PROCHOT# assertion
policies are independent of Adaptive Thermal Monitor enabling.
Note:
Bus snooping and interrupt latching are active while the TCC is active.
