Reference Board Summary
Intel
®
Atom™ Processor E660 with Intel
®
Platform Controller Hub EG20T Development Kit
User Manual
January 2012
50
Document Number: 324213-002
The carrier board has two JTAG headers. One is used for the Intel
®
PCH EG20T internal
boundary scan testing and signal monitoring in validation. The other is used the CPLD’s
firmware programming. These JTAG interfaces are not chained and each header is
different.
The Intel
®
PCH EG20T JTAG header is 1x6 2.54mm pin header (X42), and the CPLD’s
JTAG header is 2x7 2.00mm pin header (X43). See
for header location.
The CPLD’s JTAG header is only used to connect Xilinx JTAG download cable.
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