20
Specification Update
Errata
BV1.
The Processor May Report a #TS Instead of a #GP Fault
Problem:
A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication:
Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV2.
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Problem:
Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication:
Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround:
Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV3.
IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
Problem:
The IO_SMI bit in SMRAM’s location 7FA4H is set to “1” by the CPU to indicate a System
Management Interrupt (SMI) occurred as the result of executing an instruction that
reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by:
• A non-I/O instruction
• SMI is pending while a lower priority event interrupts
• A REP I/O read
• A I/O read that redirects to MWAIT
Implication:
SMM handlers may get false IO_SMI indication.
Workaround:
The SMM handler has to evaluate the saved context to determine if the SMI was
triggered by an instruction that read from an I/O port. The SMM handler must not
restart an I/O instruction if the platform has not been configured to generate a
synchronous SMI for the recorded I/O port address.
Status:
For the steppings affected, see the Summary Tables of Changes.
