Intel BX80637I53570K, Specification

Page 1: ...Reference Number 326766 Desktop 3rd Generation Intel Core Processor Family Specification Update June 2013 Revision 012 ...

Page 2: ... or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be ob...

Page 3: ...Specification Update 3 Contents Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 13 Errata 20 Specification Changes 51 Specification Clarifications 52 Documentation Changes 53 ...

Page 4: ...Contents 4 Specification Update ...

Page 5: ...d errata BV84 BV87 June 2012 005 Added Intel Pentium G2120 and G2100T Processors Added Desktop 3rd Generation Intel Core i3 3220 i3 3220T i3 3225 i3 3240 i3 3240T i5 3330 i5 3330S i5 3330P processors October 2012 006 Added errata BV88 BV91 November 2012 007 Added errata BV92 BV95 December 2012 008 Documentation Change January 2013 009 Added Errata BV96 BV97 March 2013 010 Added Errata BV98 Updated...

Page 6: ... Volume 2 326765 003 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Arc...

Page 7: ...f the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the...

Page 8: ...Plan Fix This erratum may be fixed in a future stepping of the product Fixed This erratum has been previously fixed No Fix There are no plans to fix this erratum Row Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document Errata Sheet 1 of 5 Number Steppings Status ERRATA E 1 L 1 N 0 BV1 X X X No Fix The Processor May Report a TS...

Page 9: ... System Hang BV21 X X X No Fix GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code BV22 X X X No Fix DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is Followed by a Store or an MMX Instruction BV23 X X X No Fix APIC Error Received Illegal Vector May be Lost BV24 X X X No Fix Changing the Memory Type for an In Use Page...

Page 10: ...V46 X X X No Fix Setting Hardware Autonomous Speed Disable Configuration Bit Will Block Initial Speed Upgrade BV47 X X X No Fix LTR Message is Not Treated as an Unsupported Request BV48 X X X No Fix 64 bit REP MOVSB STOSB May Clear The Upper 32 bits of RCX RDI And RSI Before Any Data is Transferred BV49 X X X No Fix An Interrupt Recognized Prior to First Iteration of REP MOVSB STOSB May Result EFL...

Page 11: ...th the VEX Prefix May Produce a NM Exception BV74 X X X No Fix VM Exits Due to NMI Window Exiting May Not Occur Following a VM Entry to the Shutdown State BV75 X X X No Fix Execution of INVVPID Outside 64 Bit Mode Cannot Invalidate Translations For 64 Bit Linear Addresses BV76 X X X No Fix PCIe Controller May Not Properly Indicate Link Electrical Idle Condition BV77 X X X No Fix PCIe Controller Ma...

Page 12: ...sults BV99 X X X No Fix The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged BV100 X X X No Fix Spurious VT d Interrupts May Occur When the PFO Bit is Set BV101 X X X No Fix Processor May Livelock During On Demand Clock Modulation BV102 X X X No Fix IA32_VMX_VMCS_ENUM MSR 48AH Does Not Properly Report The Highest Index Value Used For VMCS Encoding BV...

Page 13: ...t model See Table 1 for the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX register Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register C...

Page 14: ...0 Frequency GHz 1 Shared L3 Cache Size MB Notes SR0PQ i7 3770T E 1 000306A9h 2 5 1600 650 4 core 3 1 3 core 3 4 2 core 3 6 1 core 3 7 8 2 3 4 5 6 SR0PN i7 3770S E 1 000306A9h 3 1 1600 650 4 core 3 5 3 core 3 6 2 core 3 8 1 core 3 9 8 2 3 4 5 6 SR0PL i7 3770K E 1 000306A9h 3 5 1600 650 4 core 3 7 3 core 3 8 2 core 3 9 1 core 3 9 8 2 4 6 SR0PK i7 3770 E 1 000306A9h 3 4 1600 650 4 core 3 7 3 core 3 8...

Page 15: ...3570S N 0 000306A9h 3 1 1600 650 4 core 3 4 3 core 3 5 2 core 3 7 1 core 3 8 6 3 4 5 6 SR0T7 i5 3570 N 0 000306A9h 3 4 1600 650 4 core 3 6 3 core 3 7 2 core 3 8 1 core 3 8 6 3 4 5 6 SR0TA i5 3470S N 0 000306A9h 2 9 1600 650 4 core 3 2 3 core 3 3 2 core 3 5 1 core 3 6 6 3 4 5 6 SR0T8 i5 3470 N 0 000306A9h 3 2 1600 650 4 core 3 4 3 core 3 5 2 core 3 6 1 core 3 6 6 3 4 5 6 SR0RR i5 3330S E 1 000306A9...

Page 16: ...SR0P5 E3 1240V2 E 1 000306A9h 3 4 1600 0 4 core 3 6 3 core 3 7 2 core 3 8 1 core 3 8 8 2 3 4 5 6 SR0P4 E3 1230V2 E 1 000306A9h 3 3 1600 0 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 7 8 2 3 4 5 6 SR0PJ E3 1225V2 E 1 000306A9h 3 2 1600 650 4 core 3 4 3 core 3 5 2 core 3 6 1 core 3 6 8 3 4 5 6 SR0PH E3 1220V2 E 1 000306A9h 3 1 1600 4 core 3 3 3 core 3 4 2 core 3 5 1 core 3 5 8 3 4 5 6 SR0R6 E3 1220LV2...

Page 17: ...4 5 6 SR0TJ i5 3335S E 1 000306A9h 2 7 1600 650 4 core 2 8 3 core 2 9 2 core 3 1 1 core 3 2 6 4 5 6 SR0WS i5 3350P E 1 000306A9h 3 1 1600 4 core 3 1 3 core 3 2 2 core 3 3 1 core 3 3 6 4 5 6 SR0UF G2120 P 0 000306A9h 3 1 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 1 3 4 SR0UJ G2100T P 0 000306A9h 2 6 1600 650 4 core N A 3 core N A 2 core N A 1 core 2 6 3 4 SR0RF i3 3225 L 1 000306A9h 3 3 160...

Page 18: ...2 5 3 4 SR10H G2020 P 0 000306A9h 2 9 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 9 3 4 SR10J G2010 L 1 000306A9h 2 8 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 8 3 4 SR10K G1610 P 0 000306A9h 2 6 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 6 2 4 SR10L G1620 P 0 000306A9h 2 7 1333 650 4 core N A 3 core N A 2 core N A 1 core 2 7 2 4 SR10M G1610T P 0 000306A9h 2 3 1333 650 4 co...

Page 19: ...core N A 1 core 3 5 3 2 4 SR0YL i3 3245 L 1 000306A9h 3 4 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 4 3 2 4 SR0YT G2140 P 0 000306A9h 3 3 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 3 3 4 SR0YV G2120T P 0 000306A9h 2 7 1600 650 4 core N A 3 core N A 2 core N A 1 core 2 7 3 4 SR163 G2030 N 0 000306A9h 3 1600 650 4 core N A 3 core N A 2 core N A 1 core 3 3 4 SR164 G2030T P 0 000306A9...

Page 20: ...ry type UC the data size of each write will now always be 8 bytes as opposed to the original data size WP the data size of each write will now always be 8 bytes as opposed to the original data size and there may be a memory ordering violation WT there may be a memory ordering violation Workaround Software should avoid crossing page boundaries from WB or WC memory type to UC WP or WT memory type wi...

Page 21: ...T Status For the steppings affected see the Summary Tables of Changes BV6 Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem Performance Monitor Event FP_MMX_TRANS_TO_MMX Event CCH Umask 01H counts transitions from x87 Floating Point FP to MMX instructions Due to this erratum if only a small number of MMX instructions including EMMS are executed immediately aft...

Page 22: ...rtial memory state restore of the FXRSTOR or XRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16 bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32 bit mode Implication FXSAVE FXRSTOR or XSAVE XRSTOR will incur a GP fault due to the memory limit violation as expected but the memory state may be only part...

Page 23: ...tion will produce the same results as if it had initially completed without fault or VM exit Workaround If the handler of the affected events inspects the arithmetic portion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation Status For the steppings affected see the Summary Tables of Changes BV12 B0 B3 Bits in DR6 For Non...

Page 24: ...breakpoint enable flag in DR7 is disabled Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV15 LER MSRs May Be Unreliable Problem Due to certain internal processor events updates to the LER Last Exception Record MSRs MSR_LER_FROM_LIP 1DDH and MSR_LER_TO_LIP 1DEH may happen when no update was expected Implication The values of the LER MSRs may be unrel...

Page 25: ... the steppings affected see the Summary Tables of Changes BV19 Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word Problem Under a specific set of conditions MMX stores MOVD MOVQ MOVNTQ MASKMOVQ which cause memory access faults GP SS PF or AC may incorrectly update the x87 FPU tag word register This erratum will occur when the following additional conditions are also met The MMX store...

Page 26: ...as breakpoints detected by the following instruction Due to this erratum DR6 B0 B3 bits may not contain information about data breakpoints matched during the MOV POP SS when the following instruction is either an MMX instruction that uses a memory addressing mode with an index or a store instruction Implication When this erratum occurs DR6 may not contain information about all breakpoints matched ...

Page 27: ...RRs memory type range registers specify for the physical address of the access Implication Bits 53 50 of the IA32_VMX_BASIC MSR report that the WB write back memory type will be used but the processor may use a different memory type Workaround Software should ensure that the VMCS and referenced data structures are located at physical addresses that are mapped to WB memory type by the MTRRs Status ...

Page 28: ...may be incorrect Wrapping an 80 bit FP load around a 4 Gbyte boundary in this way is not a normal programming practice Intel has not observed this erratum with any commercially available software Workaround If the FP Data Operand Pointer is used in a 64 bit operating system which may run code accessing 32 bit addresses care must be taken to ensure that no 80 bit FP accesses are wrapped around a 4 ...

Page 29: ...d None identified Status For the steppings affected see the Summary Tables of Changes BV32 Reception of Certain Malformed Transactions May Cause PCIe Port to Hang Rather Than Reporting an Error Problem If the processor receives an upstream malformed non posted packet for which the type field is IO Configuration or the deprecated TCfgRd and the format is 4 DW header then due to this erratum the int...

Page 30: ...ng IA32_FIXED_CTR2 Other than the PMI the counter programming is not affected by this erratum as the attempted write operation does succeed Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV36 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions Problem Under specific internal conditions if software tries to write the...

Page 31: ... illegal instruction Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV40 Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered Problem If the local APIC timer s CCR current count register is 0 software should be able to determine whether a previously generated timer interrupt is being delivered by first reading the delivery stat...

Page 32: ...the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BV43 Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 Problem The processor can be configured to issue a PMI performance monitor interrupt upon overflow of the IA32_FIXED_CTR0 MSR 309H A single PMI should be observed on overflow of IA32_FIXED_CTR0...

Page 33: ... Implication When this erratum occurs DR6 may not contain information about all breakpoints matched This erratum will not be observed under the recommended usage of the MOV SS r m or POP SS instructions i e following them only with an instruction that writes E R SP Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV46 Setting Hardware Autonomous Speed ...

Page 34: ...ruction breakpoints are delivered correctly despite this erratum this is because the erratum occurs only after the processor has evaluated instruction breakpoint conditions Workaround Software whose correctness depends on value saved for EFLAGS RF by delivery of the affected interrupts can disable fast string operation by clearing Fast String Enable in bit 0 in the IA32_MISC_ENABLE MSR 1A0H Status...

Page 35: ...steppings affected see the Summary Tables of Changes BV54 The RDRAND Instruction Will Not Execute as Expected Problem On processors that support the RDRAND instruction that capability should be reported via the setting of CPUID 01H ECX RDRAND bit 30 Due to this erratum that bit will not be set and the execution of the RDRAND instruction will result in a UD exception Implication Software will not b...

Page 36: ...e system Workaround VMM s should ensure that all processor graphics device interactions conform to guidance published in the Intel Open Source HD Graphics Programmer s Reference Manual and driver writers guide Status For the steppings affected see the Summary Tables of Changes BV58 An Event May Intervene Before a System Management Interrupt That Results from IN or INS Problem If an I O instruction...

Page 37: ...rcially available devices Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV61 Processor May Issue PCIe EIEOS at Incorrect Rate Problem When initiating a Secondary Bus Reset or Link Disable procedure while a PCIe Link is in Recovery state the processor should send an EIEOS Electrical Idle Exit Ordered Set after every 32 TS Training Set Ordered Sets Du...

Page 38: ...ilable add in cards Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV65 Reception of Certain Malformed Transactions May Cause PCIe Port to Hang Rather Than Reporting an Error Problem If the processor receives an upstream malformed non posted packet for which the type field is IO Configuration or the deprecated TCfgRd and the format is 4 DW header the...

Page 39: ...k cannot achieve block alignment Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV69 Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX vvvv May Produce a NM Exception Problem The VAESIMC and VAESKEYGENASSIST instructions should produce a UD Invalid Opcode exception if the value of the vvvv field in the VEX prefix is not 1111b Due...

Page 40: ...mmary Tables of Changes BV72 Successive Fixed Counter Overflows May be Discarded Problem Under specific internal conditions when using Freeze PerfMon on PMI feature bit 12 in IA32_DEBUGCTL Freeze_PerfMon_on_PMI MSR 1D9H if two or more PerfMon Fixed Counters overflow very closely to each other the overflow may be mishandled for some of them This means that the counter s overflow status bit in MSR_P...

Page 41: ...e INVVPID descriptor and invalidate translations for bits 31 0 of the linear address Implication The INVVPID instruction may fail to invalidate translations for linear addresses that set bits in the range 63 32 Because this erratum applies only to executions outside 64 bit mode it applies only to attempts by a 32 bit virtual machine monitor VMM to invalidate translations for a 64 bit guest Intel h...

Page 42: ...aracterization may result in processor hang Intel has not observed this erratum with any commercially available platforms under normal operating conditions Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV79 Unused PCIe Lanes May Report Correctable Errors Problem Due to this erratum during PCIe link downconfiguration unused lanes may report a Correct...

Page 43: ...or the graphics driver to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BV83 A PCIe Link That is in Link Disable State May Prevent DDR I O Buffers From Entering a Power Gated State Problem When entering Link Disable LTSSM state the PCIe controller may not properly indicate the Link electrical idle condition Implication An incorrect Link e...

Page 44: ... to issue a PMI performance monitor interrupt multiple PMIs may be signaled from the same overflow condition Likewise if a corresponding counter is configured in PEBS mode applies to only the general purpose counters multiple PEBS events may be signaled Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV86 RDMSR of IA32_PERFEVTSEL4 7 May Return an Inco...

Page 45: ...of a parity error found during WBINVD execution Workaround None identified Status For the steppings affected see the Summary Tables of Changes BV90 During Package Power States Repeated PCIe and or DMI L1 Transitions May Cause a System Problem Under a complex set of internal conditions and operating temperature when the processor is in a deep power state package C3 C6 or C7 and the PCIe and or DMI ...

Page 46: ...Incorrect Value for Blocking by STI in the Context of Probe Mode Redirection Problem The GETSEC instruction causes a VM exit when executed in VMX non root operation Such a VM exit should set bit 0 in the Interruptability state field in the virtual machine control structure VMCS if the STI instruction was blocking interrupts at the time GETSEC commenced execution Due to this erratum a VM exit execu...

Page 47: ...tion May Not Report the Processor Number in the Brand String for Intel Core i3 3227U and i5 3337U Processors Problem When the CPUID instruction is executed with EAX 80000002H 80000003H and 80000004H the returned brand string may be incomplete it may be missing the processor number Implication When this erratum occurs the processor may be missing the processor number in the brand string In addition...

Page 48: ...LLC_HIT_RETIRED XSNP_MISS MEM_LOAD_UOPS_LLC_HIT_RETIRED XSNP_NONE MEM_LOAD_UOPS_RETIRED LLC_MISS MEM_LOAD_UOPS_LLC_MISS_RETIRED LOCAL_DRAM MEM_LOAD_UOPS_LLC_MISS_RETIRED REMOTE_DRAM MEM_LOAD_UOPS_RETIRED L2_MISS Implication Due to this erratum certain performance monitoring event may produce unreliable results when SMT is enabled Workaround None identified Status For the steppings affected see the...

Page 49: ...or higher Status For the steppings affected see the Summary Tables of Changes BV102 IA32_VMX_VMCS_ENUM MSR 48AH Does Not Properly Report The Highest Index Value Used For VMCS Encoding Problem IA32_VMX_VMCS_ENUM MSR 48AH bits 9 1 report the highest index value used for any VMCS encoding Due to this erratum the value 21 is returned in bits 9 1 although there is a VMCS field whose encoding uses the i...

Page 50: ...olation Intel has not observed this erratum to impact the operation of any commercially available software Workaround Software requiring the page offset of the original memory access address can derive it by simulating the effective address computation of the instruction that caused the EPT violation Status For the steppings affected see the Summary Tables of Changes BV105 IA32_VMX_VMCS_ENUM MSR 4...

Page 51: ...Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new Specific...

Page 52: ...tectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new...

Page 53: ...ion Feature Clarification Software Controlled Clock Modulation section of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide will be modified to differentiate On demand clock modulation feature on different processors The clarification will state For Hyper Threading Technology enabled processors the IA32_CLOCK_MODULATION register is duplicated for e...

Page 54: ...cification Update DisplayFamily_Displa yModel DisplayFamily_Display Model DisplayFamily_Displa yModel DisplayFamily_Display Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 ...