Electrical Specifications
24
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Note:
1.
Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
Processors that support these signals will be outlined in the
Quad-Core Intel® Xeon® Processor 5300
Series Specification Update
.
2.8
CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See
Section 2.13
for the DC
specifications. See
Section 7
for additional timing requirements for entering and
leaving the low power states.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
2.10
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processor and external thermal monitoring devices. The Quad-Core
Intel® Xeon® Processor 5300 Series contains Digital Thermal Sensors (DTS)
distributed throughout the die. These sensors are implemented as analog-to-digital
converters calibrated at the factor for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control.
2.10.1
DC Characteristics
A PECI device interface operates at a nominal voltage set by V
TT
. The set of DC
electrical specifications shown in
Table 2-10
is used with devices normally operating
from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All
PECI devices will operate at the V
TT
level determined by the processor installed in the
system. For V
TT
specifications, refer to
Table 2-12
.
Table 2-9.
Signal Reference Voltages
GTLREF
CMOS
A[37:3]#
1
, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#,
BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
HIT#, HITM#, LOCK#, MCERR#, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, STPCLK#, TCK, TDI,
TMS, TRST#
Summary of Contents for E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core Processor
Page 8: ...8 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 14: ...Introduction 14 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 38: ...Electrical Specifications 38 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 48: ...Mechanical Specifications 48 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 70: ...Land Listing 70 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 96: ...Features 96 Quad Core Intel Xeon Processor 5300 Series Datasheet...
