Intel iAPX 186/188, User Manual

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Page 2: ...ooks contain data sheets application notes article reprints and other design information QUALITY RELIABILITY HANDBOOK Order No 210997 001 Contains technical details of both quality and reliability pro...

Page 3: ...iAPX 86 88 186 188 User s Manual Hardware Reference 1985...

Page 4: ...DDX iMMX Insite Intel intel intelBOS Intelevision int igent Identifier int igent Programming Intellec Intellink iOSP iPDS iRMX iSBC iSBX iSDM iSXM KEPROM Library Manager MCS Megachassis MICROMAINFRAME...

Page 5: ...nge Mechanisms 1 110 1 5 1 Minimum Mode HOLD HLDA 1 110 1 5 2 Maximum Mode RQ GT 1 113 1 6 RESET 1 118 1 6 1 Reset Bus Conditioning 1 118 1 6 2 Multiple Processor Considerations 1 119 1 7 Interrupts 1...

Page 6: ...8 4 Chip Select Wait State Generation Unit 2 74 2 8 5 Clock Generator Reset Ready 2 79 Chapter 3 8087 Numeric Processor Extension 3 1 Introduction 3 1 3 1 1 iAPX86 88 186 188Base 3 1 3 1 2 8087 Mobili...

Page 7: ...Peripherals 5 1 5 6 OSP Memory Usage 5 11 5 7 Interrupt Controller 5 12 5 7 1 Level Triggered Mode 5 12 5 7 2 Edge Triggered Mode 5 12 5 7 3 Local Interrupt Requests 5 13 5 7 4 Interrupt Sequence 5 1...

Page 8: ...terpretation of 8 Bit Numbers 2 9 2 4 Bit Manipulation Instructions 2 9 2 5 String Instructions 2 10 2 6 Program Transfer Instructions 2 10 2 7 Interpretation of Conditional Transfers 2 11 2 8 Process...

Page 9: ...2 OSP Primitives 5 6 5 3 Data Types 5 8 5 4 Mnemonic Codes for Exceptions 5 9 5 5 Baud Rate Counter Values 16X 5 11 Figures 1 1 Small 8088 Based System 1 2 1 2 8086 8088 8089 Multiprocessing System 1...

Page 10: ...ming 1 87 1 54 110 Device Chip Select Techniques 1 88 1 55 16 bit to 8 bit Bus Conversion 1 88 1 56 Bipolar PROM Decoder 1 88 1 57 16 bit I O Decode 1 88 1 58 8086 System Configurations 1 90 1 59 Devi...

Page 11: ...p Operation 1 125 1 108 NMI INTR Single Step and Divide Error Simultaneous Interrupts 1 126 1 109 8284A Clock Generator Driver Block Diagram 1 127 1 110 8086 88 Clock Waveform 1 127 1 111 Recommended...

Page 12: ...OCK Active Until Ready Is Returned 2 33 2 16 80186 8288 8289 Interconnection 2 34 2 17 Physical Memory BytelWord Addressing 2 35 2 18 80186 External Chip SelectlDevice Chip Select Generation 2 35 2 19...

Page 13: ...2 69 UMCS Register 2 77 2 70 LMCS Register 2 77 2 71 MPCS Register 2 77 2 72 MMCS Register 2 78 2 73 Clock In Clock Out Timing 2 79 2 74 80186 Clock Generator Block Diagram 2 79 2 75 Recommended iAPX...

Page 14: ...4 26 4 12 RESET CA Initialization Timing 4 27 4 13 Channel Attention Decoding Circuit 4 28 4 14 Channel Command Word Encoding 4 28 4 15 Channel Commands 4 29 4 16 Channel State Save Area 4 30 4 17 So...

Page 15: ...808618088 CPU 1...

Page 16: ......

Page 17: ...either minimum mode or maximum mode circuits 1 1 In the minimum mode the CPU is configured for small single processor systems In this configuration all control signals are provided by the CPU and the...

Page 18: ...1 3 and 1 4 These are the Execution Unit EU and the Bus Interface Unit BID Both microprocessors contain identical EU s In 1 2 the 8086 the BID incorporates a 16 bit data bus and a 6 byte instruction q...

Page 19: ...tion object code byte from the BIU s instruction queue and then executes the instruction If the queue is 1 3 empty when the EU is ready to fetch an instruction byte the EU waits for the instruction by...

Page 20: ...ctions so long as execution proceeds serially If the EU executes an instruction that transfers control to another location the BIU resets the queue fetches the instruction from the new address passes...

Page 21: ...veral instructions Good program ming practice and consideration of compatibility with fu ture Intel hardware and software products dictate that the segment registers be used in a disciplined fashion 1...

Page 22: ...ag is used by instructions that add and subtract multibyte numbers Rotate instructions can also isolate a bit in memory or a register by plac ing it in the carry flag 3 IfOF the overflow flag is set a...

Page 23: ...s these interrupts IF has no affect on either non maskable external or internally gener ated interrupts 3 Setting TF the trap flag puts the processor into single step mode for debugging In this mode t...

Page 24: ...on given to segment definition The segment structure of the 8086 8088 memory space supports modular software design by discouraging huge monolithic programs The segments also can be used to advantage...

Page 25: ...variables memory operands are assumed to reside in the current data segment although a program can instruct the BIU to access a variable in one of the other currently addressable segments The offset...

Page 26: ...de segment In other words all offsets in the program must be relative to fixed values contained in the segment registers This al lows the program to be moved anywhere in memory as long as the segment...

Page 27: ...an access either 8 or 16 bits of memory at a time If an instruction refers to a word variable and that variable is located at an even numbered address the 8086 1 11 accesses the complete word in one b...

Page 28: ...uc tions typically found in previous microprocessors such as the 8080 8085 Significant new operations include FFFFFH RESERVED FFFFCH FFFFBH DEDICATED FFFFOH FFFEFH OPEN I BOH 7FH RESERVED 14H 13H DEDI...

Page 29: ...ment a different 16 bit register Each of these instructions are only one byte long The assembly level instructions simplify the programmers view of the instruction set The programmer writes one form o...

Page 30: ...data may produce unpredictable results Arithmetic instructions post certain characteristics of the result of an operation to six flags Refer to Chapter 3 in the iAPX 86 88 186 188 User s Manual Progr...

Page 31: ...a source operand a destination operand or both The harde ware assumes that a source string resides in the current data segment A segment prefix may be used to override this assumption A destination s...

Page 32: ...segment intrasegment transfer or to a different code segment in tersegment transfer The ASM 86 Assembler terms an intrasegment transfer SHORT or NEAR and an interseg ment transfer FAR The transfer is...

Page 33: ...selves i e they are SHORT transfers d Interrupt Instructions The interrupt instructions allow interrupt service routines to be activated by programs as well as by external hard ware devices The effect...

Page 34: ...the content of an index register see Figure 1 17 Any combination of these three components may be present in a given instruction This allows a variety of memory addressing modes 1 18 The displacement...

Page 35: ...BX I g I OR EA SI 1 7 Figure 1 19 Register Indirect Addressing I 1 19 e Indexed Addressing The effective address is calculated from the sum of a dis placement plus the content of an index register SI...

Page 36: ...nt on the stack typically the top of the stack after the procedure has saved registers and allocated local storage The offset of the beginning of the array from the reference point can be expressed by...

Page 37: ...hat adjusts the value of DX Instruction timings are presented as the number of clock periods required to execute a particular form of the in struction register to register immediate to memory etc If t...

Page 38: ...hich control is to be transfer red indirectly A label to which control is to be conditionally transferred must lie within 128 to 127 bytes of the first byte of the next instruction Register AX for wor...

Page 39: ...d be added to the y part of the expression before it is multiplied by the number of repetitions Several additional factors can alter the actual execution time from the figures shown in Table 1 16 The...

Page 40: ...he figures provided in the table The execution time for a given sequence of instructions is always repeatable as smning comparable external conditions interrupts co processor activity etc Ifthe execut...

Page 41: ...Operands Clocks Transfers Bytes Coding Example register register 3 3 2 ANDAL BL register memory 9 10 EA 1 2 4 AND CX FLAB WORD memory register 16 10 EA 2 2 4 AND ASCII DI AL register immediate 4 4 3 4...

Page 42: ...BX CX register memory 9 10 EA 1 2 4 CMP DH ALPHA memory register 9 10 EA 1 2 4 CMP BP 21 SI register immediate 4 3 EA 3 4 CMP BL 02H memory immediate 10 10 EA 1 3 6 CMP BXI RADAR 01 3420H accumulator...

Page 43: ...2 DIVCL reg 16 144 162 38 2 DIVBX mem8 86 96 EA 1 2 4 DIVALPHA 35 mem 16 150 168 1 2 4 DIV TABLE SI EA 94 ENTER IENTER Flags ODITSZAPC Procedure entry Operands Clocks Transfers Bytes Coding Example l...

Page 44: ...31 34 mem 16 134 160 1 2 4 IMUL RATE_WORD BP 01 EA 40 43 IN liN accumulator port Flags ODITSZAPC Input byte or word Operands Clocks Transfers Bytes Coding Example accumulator immed 8 10 10 1 2 IN AL O...

Page 45: ...gs OOITSZAPC Jump if above Jump if not below nor equal Operands Clocks Transfers Bytes Coding Example Short label 16 or 2 JAABOVE 4 13 or 4 JAE JNB I JAE JNB short label Flags 00 I TSZAPC Jump if abov...

Page 46: ...Operands Clocks Transfers Bytes Coding Example short label 16 or 2 JG GREATER 4 13 or 4 JGE JNL IJGE JNL short label Jump if greater or equal Jump if not less Flags 0 0 ITS ZAP C Operands Clocks Tran...

Page 47: ...short label 16 or 2 JNE NOT_EQUAL 4 13 or 4 JNO IJNO short label Jump if not overflow Flags OD I TSZAPC Operands Clocks Transfers Bytes Coding Example short label 16 or 2 JNO NO_OVERLOW 4 13 or 4 JNP...

Page 48: ...16 116 18 EAI 2 1 2 4 LDS SI DATA SEG DI LEA ILEA destination source Flags OD I TSZAPC Load effective address Operands I Clocks ITransfers 1Bytes Coding Example reg 16 mem 16 I 2 6 EA 1 r 2 4 LEA BX B...

Page 49: ...INMI external nonmaskable interrupt Flags 00 I TSZAPC Interrupt if NMI 1 00 Operands Clocks Transfers Bytes Coding Example no operands 50 5 N A N A MOV IMOV destination source Flags ODITSZAPC Move Op...

Page 50: ...nds Clocks Transfers Bytes Coding Example reg 8 70 77 2 MULBL 26 28 reg 16 118 133 2 MULCX 35 37 mem8 76 83 1 2 4 MUL MONTH 51 EA 32 34 mem 16 124 139 1 2 4 MUL BAUD_RATE EA 41 43 NEG INEG destination...

Page 51: ...urce string 14 2 1 OUTS PORT2 BUFF2 repeat port source string 8 8 rep 2 rep 1 REP OUTS PORT2 BUFF2 POP IPOP destination Flags OOITSZAPC Pop word off stack Operands Clocks Transfers Bytes Coding Exampl...

Page 52: ...2 2 Clocks Transfers 2 2 8 41 bit 5 1 bit 15 15 EA 20 41 bit 17 1 bit EA 5 1 bit 17 1 bit IREP no operands Repeat string operation 2 2 2 Clocks Transfers 2 2 REPE REPZ no operands Bytes 2 2 2 4 2 4 3...

Page 53: ...2 ROL BX 1 register CL 8 41 2 ROLOI CL bit 5 1lbit memory 1 15 15 EA 2 2 4 ROL FLAG_BYTE 01 1 memoryCL 20 41 2 2 4 ROL ALPHA CL bit 17 1 bit EA register n 5 1 bit 3 ROLBX 5 memory n 17 1 bit 2 3 5 ROL...

Page 54: ...20 41 2 2 4 SAR N_BLOCKS CL bit 17 1 bit EA register n 5 1 bit 3 SAR OX 5 memory n 17 1 bit 2 3 5 SAR OGLTH 5 SBB ISBB destination source Subtract with borrow FI 0 0 ITS ZAP C ags X XXXXX Operands Cl...

Page 55: ...Transfers Bytes Coding Example no operands 50 5 N A N A STC ISTC no operands Flags ODITSZAPC Set carry flag C Operands Clocks Transfers Bytes Coding Example no operands 2 2 1 STC STO ISTD no operands...

Page 56: ...Operands Clocks Transfers Bytes Coding Example register register 3 3 2 TESTSI DI register memory 9 10 EA 1 2 4 TEST SI END_COUNT accumulator immediate 4 3 4 2 3 TEST AL 001000008 register immediate 5...

Page 57: ...hown in Figure 1 28 The first six bits of a multibyte instruction generally con tain an opcode that identifies the basic instruction type ADD XOR etc The following bit called the 0 field generally spe...

Page 58: ...ry oper and and or the actual value of an immediate constant operand The displacement value may contain one or two bytes the language translators generate one byte whenever possible The MOD field indi...

Page 59: ...eristics tables 1 43 BX 08 BX 016 1 3 3 OPERATING MODES One of the unique features the 8086 and 8088 CPU s al low the user is the ability to select between two functional definitions of a subset of th...

Page 60: ...P CMP b f r m w t r m b t r m w t r rn DEC DEC DEC DEC AX CX OX BX POP POP POP POP AX CX OX BX JS JNS JPI JNPI JPE JPO MOV MOV MOV MOV b fJ m w f rfm b l r m w l r m CBW CWO CAll WAIT I d TeST TeST ST...

Page 61: ...ional S or 16 bit unsigned displacement MOD indicates if present High order byte of optional 16 bit unsigned displacement MOD indicates if present Low order byte of new IP value High order byte of new...

Page 62: ...megabyte memory space 64K byte 1 0 space and 16 bit data path The CPU directly provides all bus con trol DT R DEN ALE M IO commands RD WR INTA and a simple CPU preemption mechanism Table 1 22 8086 88...

Page 63: ...1 0 0 1 1 111 SAHF Store AH into flags 1 0 0 1 1 1 1 a PUSHF Push flags 1 0 0 1 1 1 a a POPF Pop lIags 1 0 0 1 1 1 0 1 ARITHMETIC ADO Add Reg memory with register to either OOOOOOdw mod reg rim DISP L...

Page 64: ...LO DISP HI Immediate with register memory 100000sw mod rim DISP LO DISP HI data 1data if s w l J Immediate with accumulator o 0 1 1 1 lOw data AAS ASCII adjust lor subtract o 0 OAS Decimal adjust tor...

Page 65: ...mmediate data and register memory 1 1 1 1 0 1 w mod o 0 0 1m DISP LO I DISP HI j data I data it w l I Immediate data and accumulator 1010100w data OR Or Reg memory and register to either 0000lQdw mod...

Page 66: ...greater JNBIJAE Jump on not belowIabove or equal JN8E JA Jump on not below or equal above JNP JPO_Jumpon not par parodd JNO Jump on not overflow 76543210 765432 O 76543210 76543210 76543210 78543210...

Page 67: ...Set carry etD Clear direction STD Set direction eLi Clear mterrupt STI Set interrupt HLT Halt WAIT Wait ESC Escape to extern 1 device LOCK Bus lock prefix SEGMENT Override prefix I 76543210 78543210 7...

Page 68: ...ed to the bus cycle activity This mechanism 1 allows a co processor to detect execution of an ESCAPE instruc tion which directs the co processor to perform a specific task and 2 allows ICETM 86 to tra...

Page 69: ...HI SBB REG16 REG161 MEM16 1C 0001 1100 DATA B SBB AL IMMEDB 10 0001 1101 DATA LO DATA HI SBB AX IMMED16 1E 0001 1110 PUSH OS 1F 0001 1111 POP OS 20 0010 0000 MOD REG RIM DISP LO DISP HI AND REGB MEMB...

Page 70: ...0 INC DX 43 0100 0011 INC BX 44 0100 0100 INC SP 45 0100 0101 INC BP 46 0100 0110 INC SI 47 0100 0111 INC DI 48 0100 1000 DEC AX 49 0100 1001 DEC CX 4A 0100 1010 DEC DX 4B 0100 1011 DEC BX 4C 0100 110...

Page 71: ...JNGE SHORT LABEL 70 0111 1101 IP INC8 JNLlJGE SHORT LABEL 7E 0111 1110 IP INC8 JLE JNG SHORT LABEL 7F 0111 1111 IP INC8 JNLE JG SHORT LABEL 80 1000 0000 MOD 000 RIM DISP LO DISP HI ADD REG8 MEM8 IMMED...

Page 72: ...D010 RIM DISP LO DISP HI ADC REG161 MEM16 IMMED8 DATA SX 83 1000 0011 MOD011 RIM DISP LO DISP HI SBB REG16 MEM16 IMMED8 DATA SX 83 1000 0011 MOD 100 RIM not used 83 1000 0011 MOD101 RIM DISP LO DISP H...

Page 73: ...V AX MEM16 A2 1010 0010 ADDR LO ADDR HI MOV MEM8 AL A3 1010 0011 ADDR LO ADDR HI MOV MEM16 AL A4 1010 0100 MOVS DEST STR8 SRC STR8 A5 1010 0101 MOVS DEST STA16 SRC STR16 A6 1010 0110 CMPS DEST STR8 SR...

Page 74: ...ed C7 1100 0111 MOD010R M not used C7 1100 0111 MOD011 RIM not used C7 1100 0111 MOD 100 RIM not used C7 1100 0111 MOD101 RIM not used C7 1100 0111 MOD110R M not used C7 1100 0111 MOD 111 RIM not used...

Page 75: ...EM16 CL 03 1101 0011 M00100 RIM OISP LO OISP HI SALISHL REG16 MEM16 CL 03 1101 0011 M00101 RIM OISP LO OISP HI SHR REG16 MEM16 CL 03 1101 0011 MOD 110 RIM not used 03 1101 0011 M00111 RIM OISP LO OISP...

Page 76: ...EG16 MEM16 F7 1111 0111 MOD101 RIM DISP LO DISP HI IMUL REG16 MEM16 F7 1111 0111 MOD110 RIM DISP LO DISP HI DIV REG16 MEM16 F7 1111 0111 MOD 111 RIM DISP LO DISP HI IDIV REG16 MEM16 F8 1111 1000 CLC F...

Page 77: ...riented devices tied to the upper half of the bus 0 0 Whole word would normally use SHE to condition chip select func 0 1 Upper byte froml tions SHE is LOW during T for read write and inter to odd add...

Page 78: ...0 Write 1 0 Port the beginning of a bus cycle and the return to the pas 0 1 1 Hall sive state in T3 or Tw is used to indicate the end of a bus 1 HIGH 0 0 Code Access cycle 0 1 Read Memory 1 1 0 Write...

Page 79: ...e cy cle It is active LOW and floats to 3 state OFF in local bus hold acknowledge INTA 24 0 INTA is used as a read strobe for interrupt acknowledge cycles It is active LOW during T2 T3 and Tw of each...

Page 80: ...pted LOCK remains active Further information on the oper ation of an interrupted string operation with multiple pre fixes is presented in the section dealing with the 8086 interrupt structure 1 64 1 3...

Page 81: ...1 40 The minimum bus cycle consists of four CPU clock cycles T states During the first T state Tl the CPU asserts an address on the twenty bit multi plexed addressldatal status bus For the second T s...

Page 82: ...bus during a read cycle On termination of the command the device latches write data or disables its bus drives The only way the device controls the bus cycle is by inserting wait cycles The 8086 CPU o...

Page 83: ...BHE to S7 That is if BHE is high during T I then S7 will like wise be high during T2 through T4 Since BHE is a mul tiplexed signal with timing identical to the A19 A16 address lines it also should be...

Page 84: ...10 60 10 100 ns TALAH AD Width 2TCLCL 75 2TCLCL 40 2TCLCL 50 ns TWLWH WAWidth 2TCLCL 60 2TCLCL 35 2TCLCL 4O ns TAVAL Address Valid to TCLCH 60 TCLCH 35 TClCH 4O ns ALE Low TOLOH Output Aise Time 20 2...

Page 85: ...Complexity System MAX MODE SYSTEM USING 8288 BUS CONTROLLER TIMING REQUIREMENTS T t Symbol Paramater 8086 8088 1 Preliminary 8088 2 Preliminary Unit Condition Min Max Min Max Min Max TClCl ClK Cycle P...

Page 86: ...TCLMCH ClK low to MCE 15 15 15 ns High See Note 1 TCHll ALE Inactive Delay 15 15 15 ns CL 20 100 pF SoeNotel for an 8086 Out TCLMCl MCE Inactive Delay 15 15 15 ns puts In addi SooNotel tion to 8086 se...

Page 87: ...e entire 16 bit data bus even though data is only expected on the upper or lower half of the data bus As will be demonstrated later this action simplifies the chip select decoding require ments for re...

Page 88: ...READ CYCLE INOTE 1 RD cWJt iNTi VOH OTIR rCLAV I TCLDV _ i TCHDX TCLAX iRE A1 A 57 53 I TCLlH f TLHLl _TLLAX I I I I r I _ TAL _ DC TCHLL I TR1VCt V H VIL I_CLRIX I I TR r I I I I I I TCHRYX TAVAL TRY...

Page 89: ...H and VOL unless otherwise specified TCVCTX SOFTWARE HALT 2 ROY is sampled near the end of T2 T3 Tw to determine if Tw machines states are to be inserted 3 Two INTA cycles run back to back The 8086 LO...

Page 90: ...SEe NOTES 5 6 RD DTIR DEN I J TClAV XI TCHCl _TClCH_ f TCHSV TClSH VI I flY SEE NOTE 81 t rCLAV CLDV TCHDX TClAX X BHE A I A I x 57 3 TSVlH TCHLL TCllH k TR1VCl t X TRYlCl_ TRYHSH I 0 TCHRYX TClAX I...

Page 91: ...2 ADY is sampled near the end of T2 T3 Tw to determine if Tw machines states are to be inserted 3 Cascade address is valid between first and second INTA cycle 4 Two INTA cycles run back to back The 8...

Page 92: ...ank 07 00 of 512K 8 bit bytes addressed in parallel by the processor s address lines A19 A1 Byte data with even addresses is transferred on the 07 00 bus lines while odd addressed byte data AO HIGH is...

Page 93: ...HE r I I II J IL JT I L oe II 8286 I i A I I TRAN EIVER I v D TUS FO OR ED I I DATA BUS DRIVE L ___I Figure 1 34 8086 88 Minimum Mode System t ClK MNIMX 4 GND MRDC ClK SO SO MWTC f READY 51 S 8288 AMW...

Page 94: ...CK LOCK NOP BYTE NEXT LOCK LOCKED INSTRUCTION PREFIX FROM THE PREFIX FROM BYTE FROM QUEUE THE QUEUE aUEUE LOCKED NOP 1 QUEUE STATUS INDICATES FIRST BYTE OF OPCODE FROM THE QUEUE 2 THE LOCK OUTPUT WILL...

Page 95: ...110 section are also applicable to these devices The relationship of parameters is given in Table 1 32 TACC and TCE are related to the same equation and differ only by the delay associated with the c...

Page 96: ...tion techniques for devices with chip selects and output enables In the first examples see Figure 1 48 AO and BHE must be included to decode or enable the chip selects Since these memories do not have...

Page 97: ...CDLVmax TCLMHmin TIVOVmax 265ns TDH TCLCH TCLMHmax TCHDXmin TIVOVmin 95ns A comparison of these results with the 2148 family indi cates the standard 2148 write timing is fully compatible with this 808...

Page 98: ...CC Address to Valid Data 5 TAVDV TCE Chip Enable to Valid Data TSLDV TDF Output Enable High to Output Float TRHDZ a Read Cycle For no wait state operation the 8086 requires data to be valid from MRDC...

Page 99: ...up time is to WE For the 8202 the WR to CAS delay is analyzed to de termine the data setup time to CAS inherently provided by the 8202 command to RAS CAS timing The mini mum delay from WR to CAS is CH...

Page 100: ...onfiguration TCCmin tph 2tp 25 127 ns 25 MHz Subtracting buffer delays and data setup at the 2118 we have 83 ns to generate valid data after the write command is issued by the CPU in this case the 828...

Page 101: ...one or two wait states 1 85 Unless 2118 3 s are used in 64K byte or less memories SACK must not be used since it does not guarantee a wait state From the previous access time analysis we saw that oth...

Page 102: ...nput to select registers within a specific device If a device on the upper half of the bus and one on the lower half are assigned addresses that differ only in AO adja 1 86 cent odd and even addresses...

Page 103: ...RING TIMINO OF DOUT I to IS MEASURED TO lOUT I OLI e IDS AND tOM ARE REFERENCED TO fii OR Wi WHICHEVER OCCURS LAST t lReM IS R FERENCED TO HE TRAILING EDGE OF CD OR m WHICHEVER OCCURS FIR8T tcRf REQUI...

Page 104: ...ction To guarantee the device is selected only for word operations AO and BHE should be conditions of chip select code see Figure 1 57 110 DEVICE COMPATIBILITY Compatibility of an I O device with a mi...

Page 105: ...uffering The last configuration is characteristic of a multi board system with bus buffers on each board The 5 MHz parameter values for these configurations re 1 89 Table 1 36 Peripherals Cycle Depend...

Page 106: ...ns delay the result is TAVDV 322 ns 5 MHz This result gives the address to data valid delay required at the peripheral in this configuration to satisfy zero wait state CPU access time If the maximum d...

Page 107: ...empty the input buffer and enable the device to input additional characters 1 91 0 ____________ 0 0 0 DEVICES ARE CONNECTED TO THE UPPER AND LOWER HALVES OF THE DATA BUS ADDRESS o 1 2 3 4 5 6 7 ETC D...

Page 108: ...be considered when referring to the system data bus 1 the multiplexed addressldata bus see Figure 1 64 and 2 a data bus buf fered from the multiplexed bus by transceivers see Fig ure 1 65 If memory o...

Page 109: ...enables To guarantee the specified A C characteristics the 8086 s drive capability of 2 0 rnA and capacitive loading of 100 pF subsequently limits the fan out of the multiplexed bus Assuming capaciti...

Page 110: ...p select will drive the bus simultaneously with write data being driven through the transceivers by the CPU see Figure 1 73 The same technique given for circumventing these prob lems on the multiplexe...

Page 111: ...E IN TRANSMIT RATHER THAN RECEIVE MODE AND WILL NOT DRIVE AGAINST THE CPU Figure 1 71 Bus Transceiver Control T 4 _ FLOAT V i FLOAT II may be either inverting or non inverting These devices propagate...

Page 112: ...R is inverted to provide proper direction con trol for the second level transceivers Another technique see Figure 1 78 provides control for devices with output enables RD is used to normally direct d...

Page 113: ...ULTIBUS system bus or an ex tension of the system bus Arbitration logic consists of the major addition required to the demultiplexed system bus MEMORY IIO DEVICES Figure 1 77 Controlling System Transc...

Page 114: ...cription earlier in this chapter When the lock prefix is decoded by the EU the EU in forms the BID to activate the LOCK output during the next clock cycle This signal remains active until one clock cy...

Page 115: ...19 16 immediately switch from address to status for both read and write cycles TLHLLmin which takes precedence over the value obtained by relating TCLLHmax and TCHLLmin guarantees the minimum ALE puls...

Page 116: ...TCHCL _TCLCH_ TCLAV TCLAX TfLDV TCHDX lilt A A 57 Sa TCLLH rTLHLL I T LAX r I TCHLL I 4 _TR1VCL TAVAL VIH X I V L _f I TCLR X R R I I I FCHRYX TAVAL TCLAV TRYHCH TLLAX I TCLAX TDVCL __ TCLDX Au Ao DAT...

Page 117: ...1 t V r 7 4 Rr L OH DEN SOFTWARE HALT _ DEN VOL lID VA 1liTA DT Ii VOH AD AD T S FOllOW TI THEN NMI OR INTR BEGIN A NEW TI AD1S ADo TCVCTV_V TCVCTX t r _ _ _ _ _ J r INVALID ADDRESS TClAV j r NOTES 1...

Page 118: ...6 8088 CPU T T T TCLCL TCH1CH21H TCL2CLl f J 1 1 TCHCL _TCLCH_ l TCHSV TCLSH W 1SEj NOTE 8 r TCLAV CLOV TCHOX TCLAX 1 ii HE A A1I 57 53 TCHLL r 1 I TR1VCL TCLR1 TRYLCL f TYHSH I TCHRYX TRYHCHzf F TCLA...

Page 119: ...END OF T2 T3 Tw TO DETERMINE IF Tw MACHINES STATES ARE TO BE INSERTED S CASCADE ADDRESS IS VALID BETWEEN FIRST AND SECOND INfA CYCLES 10TH INTA CYCLES RUN BACK To IACK THE I0Il LOCAL ADDRIOATA BUS IS...

Page 120: ...the cy cle after T4 of the INTA cycle This sequence occurs for each of the INTA bus cycles The interrupt type number read by the 8086 on the second INTA bus cycle must satisfy the same setup and hold...

Page 121: ...the 58 ns ALE enable delay The address is guar anteed to be valid TCLCHmin TCHLLmin TCLAV max 8 ns prior to the trailing edge of ALE to capture the address in the latches Again we have assumed a very...

Page 122: ...to INTA command active The selected device on the local bus must disable the system data bus transceivers since DEN is still generated by the 8288 If the 8288 is not in the lOB I O Bus mode the 8288 M...

Page 123: ...se stated for the minimum mode To inform the 8288 of HALT status when a HALT instruc tion is executed the 8086 will initiate a status transition from passive to HALT status The status change will caus...

Page 124: ...n using this approach The 8086 has two different timing requirements on READY depending on the system implementation for a normally ready system to insert a wait state the READY must be disabled withi...

Page 125: ...one clock cycle for the second BIU opcode fetch to complete and for the third byte of the MOV immediate instruction to be come availa ble for execution recall that the queue status lines indi cate que...

Page 126: ...een itself and other devices capable of acting as bus masters The minimum mode configuration offers a signal level handshake similar to the 8080 and 8085 systems The maximum mode provides an enhanced...

Page 127: ...AX SI ADD SI 8086H JMP 14 B802F8 50 8BCB 8BD1 0304 81C68680 EBFO Figure 1 93 Instruction Loop Sequence 1 111 ing to sample HOLD float the bus and enable disable HLDA relative to the CPU clock To guar...

Page 128: ...e BIU will not ac knowledge a HOLD request between the two bus cycles This type of transfer would extend the above maximum latency by four additional clocks plus N additional wait states With no wait...

Page 129: ...of the protocol and its purpose within the system architecture The maximum mode RQ OT sequence is intended to transfer control of the CPU local bus between the CPU and alternate bus masters which res...

Page 130: ...next low to high clock edge Since the 8086 can respond with a grant pulse in the clock cycle immediately following the request the RQ GT line may not return to the positive level be tween the request...

Page 131: ...inimum mode result minus 476 ns Ifthe 8086 has previously issued a grant on one of the RQ GT lines a request on the other RQ GT line will not receive a grant until the first de vice releases the inter...

Page 132: ...he AEN signal to the 8284 disables the ready input and forces a bus cycle initi ated by the 8086 to wait until the 8086 regains control of the system bus The CPU may actively drive its local mul tiple...

Page 133: ...teristics of the requesting device any of the 74LS74 outputs can be used to generate a HLDA to the device CHANNEL 0 TO 1 CLOCK Upon completion of its bus operations the alternate bus master must relin...

Page 134: ...LOW at which time the internal CPU registers are initial ized to the reset condition see Figure 1 102 Upon RESET the code segment register and the instruc tion pointer are initialized to FFFFH and 0...

Page 135: ...Table 1 41 If the reset occurs during a bus cycle the return of the status lines to the passive state will terminate the bus cycle and return the command lines to the inactive state NOTE The 8288 doe...

Page 136: ...d the hardware non maskable interrupt NMI The next 27 in terrupt vectors are reserved by Intel and should not be used to ensure compatibility with future Intel products The remaining interrupt vectors...

Page 137: ...used to allow software single stepping through a sequence of code Sin gle stepping is initiated by copying the flags onto the stack setting the TF bit on the stack and popping the flags The interrupt...

Page 138: ...of the instruction they precede the 8086 will not sample the interrupt line until completion of the instruction the prefix es pre cede s Other than HALT or WAIT the string primitives preceded by the r...

Page 139: ...a byte on the data bus that identifies the source of the interrupt the vector number or vector type This byte is read by the CPU and then multiplied by four and the resultant value used as a pointer...

Page 140: ...e transfer of control the CPU pushes the flags and current code segment register and instruc tion pointer onto the stack The new code segment and instruction pointer values are loaded and the single s...

Page 141: ...occur simultaneously while in Figure 1 108 NMI INTR and a divide error all occur during a divide instruction being single stepped 1 8 SUPPORT COMPONENTS The following paragraphs provide descriptions o...

Page 142: ...ded for a more accurate and stable frequency generation When selecting a crystal for use with the 8284A the series resistance should be as low as possible Since the other circuit com ponents will tend...

Page 143: ...tor signal used to drive the CPU clock generator circuit Because of this inversion the oscillator output of one 8284A should not drive the EFI input of a second 8284A if both are driving clock inputs...

Page 144: ...C and CLK and 22 ns between CLK and PCLK ClK 5 lK EXTERNAL SYNC I TO CSYNC INPUT CONDITION IiXTERNAl FREQUENCY TO L E F I INPUT Figure 1 115 Synchronizing CSYNC With EFI Since the state of the 8284A d...

Page 145: ...ock 5 100Q elK 8284 100Q 100Q Figure 1 119 Buffering the 8284 ClK Output input high Voltage see Figure 1 119 A single 8284A should not be used to generate the CLK for multiple CPU s that do not share...

Page 146: ...he reset has no effect on any clock circuits in the 8284A 1 8 2 8288 Bus Controller The 8288 Bus Controller Figure 1 124 uses the S2 SI and SO status bit outputs from the CPU and the 8089 lOP to gener...

Page 147: ...1 0 Write I O Port 10WC AIOWC 0 1 1 Halt None 1 0 0 Code Access M RoC 1 0 1 Read Memory MRDC 1 1 0 Write Memory MWTC AMWC 1 1 1 Passive None 1 131 and static RAMs The normal write provides data setup...

Page 148: ...IVE IN THE STATE READY MN MODE 8088 ClK 8284 OUTPUn 9 WAIT READY Figure 1 125 Status Line Activation And Termination TCVCTX 110 ns MX MODE TClMH 35 8088 OR AIllWil hl WITH 8288 Figure 1 126 Maximum an...

Page 149: ...stence and issues commands as though it has exclusive use of the system bus If the processor does not have the use of the multi master system bus the bus arbiter prevents the bus controller the data t...

Page 150: ...bus mode If both strapping options are strapped false a third mode of operation is created the single bus mode in which the arbiter interfaces the proc essor to a multi master system bus only See Fig...

Page 151: ...eration to insure correct interrupt vectoring when used in an 8086 8088 system When programmed in the MCS 86 88 mode the 8259A should only be used with an MCS 86 or MCS 88 system In this mode the 8086...

Page 152: ...interrupt vector byte for 8086 8088 type selection is put on the data bus during the second INTA pulse and shown in Figure 1 135 INTERRUPT PRIORITIES A variety of modes and commands are available for...

Page 153: ...be explained in greater detail shortly In the fully nested mode while an ISR bit is set all fur ther requests of the same or lower priority are inhibited from generating an interrupt to the microproce...

Page 154: ...The following programming conditions can cause the 8259A to go out ofthe high to low priority structure of the fully nested mode A slave with a master not in the special fully nested mode The automat...

Page 155: ...ines in service is finished b Specific EOI Command A specific EOI command is sent from the microprocessor to let the 8259A know when a service routine of a particu lar interrupt level is completed Unl...

Page 156: ...these methods is done during the programmed initialization of the 82S9A Level Triggered Mode When the 82S9A is in the level triggered mode it will recognize any active high level on the IR input as a...

Page 157: ...ignated by a high on the SP EN pin while the SP EN pins on the slaves are grounded this can also be done by software see the buffered mode Also the INT output pin of each slave is connected to the an...

Page 158: ...de The buffered mode is useful in large systems where buf fering is required on the data bus Although not limited to cascading the buffered mode is most pertinent for this use In the buffered mode whe...

Page 159: ...as not yet returned an acknowledge The 8237 may still be programmed until it receives HLDA from the RESET READY CLOCK DSTB ilili ow DREOO OREQ3 HRQ DACKO OACK3 CPU An acknowledge from the CPU signals...

Page 160: ...mented and the address decremented of incremented fol lowing each transfer When the word count rolls over from zero to FFFFH a Thrminal Count TC will cause an Autoinitialization if the channel has be...

Page 161: ...hen the word count of the channel goes to FFFFH a TC is generated causing an EOP output terminating the service To allow a single word to be writ ten to a block of memory Channel 0 may be programmed t...

Page 162: ...bits 1 Temporary Word Count Aeglster 16 bits 1 Stetul Aeglster 8blts 1 Command Register 8 bits 1 Temporary Register 8 bits 1 Mode Registers 6 bits 4 Mask Aeglster 4 bits 1 Aequest Register 4 bits 1 wr...

Page 163: ...ure 1 144 Software Command Codes 7 6 5 4 3 2 1 0 Bit Number l I I I I I I I T LfOO o 01 Channel 1 select 10 Cha el 2 s ec 11 Channel 3 select 00 Verdy transfer 01 Write transfer 10 Read transfer 11 lI...

Page 164: ...are set whenever their corresponding chan nel is requesting service Temporary Register The Temporary register is used to hold data during memory to memory transfers Following the completion of the tr...

Page 165: ...80186180188 CPU 2...

Page 166: ......

Page 167: ...runching capabilities of that device 2 2 1 Architectural Overview The 80186 188 device architecture consists of the same Bus Interface Unit BIU and Execution Unit EU as the 8086188 see Figure 2 1 The...

Page 168: ...R AOO A 6 53 REGISTERS Il l L REGISTERS uh1 L kS6 A2 LCS PCSSlA1 DTIII BHElS7 AD15 A191S6 CLKOUT Vee GHD rO J j ExEcUTIONuNrr x x I 16 BIT I ALU I CLOCK I GENERATOR I l6 BIT GENERAL I PURPOSE I REGIST...

Page 169: ...terrupt the CPU after a specified number of timer events The third timer counts only CPU clocks and can be used to interrupt the CPU after a 2 3 programmable number of CPU clocks to give a count pulse...

Page 170: ...formance results from the enhancements made to both the general and specific areas of CPU operation These include faster effective address calculation improvements in the execution speed of many instr...

Page 171: ...e bit shift can be performed or a multiple shift can be performed where the number of bits to be shifted is specified in the CL register All of the shift rotate instructions of the 80186 allow the num...

Page 172: ...of the procedure and can be as great as 255 The 80186 includes the LEAVE instructions to tear down stack frames built by the ENTER instruction As can be seen from the layout of the stack left by the...

Page 173: ...o different re quirements efficiency and simplicity The approximately 300 forms of machine level instructions make very effi cient use of storage For example the machine instruc tions that increments...

Page 174: ...with carry INC Increment byte or word by 1 AAA ASCII adjust for addition DAA Decimal adjust for addition SUBTRACTION SUB Subtract byte or word SBB Subtract byte or word with borrow DEC Decrement byte...

Page 175: ...t carry instruction String Instructions The string instructions also called primitives allow strings of bytes or words to be operated on one element byte or word at a time Strings of up to 128k bytes...

Page 176: ...egment and within 128 to 127 bytes of the first byte of the next instruction IMP DOH jumps to the first byte of the next instruction Since jumps are made by adding the relative displacement of the tar...

Page 177: ...re interrupts is similar to hardware initiated interrupts However the processor does not execute an interrupt acknowledge bus cycle if the interrupt originates in software or with an NMI High Level In...

Page 178: ...affect the device reliability Table 2 11 presents the D C voltage characteristics of the 80186 188 CPU s Tables 2 12 through 2 16 list the vari ous A C characteristics timing requirements and timing r...

Page 179: ...g I Segment register 10 0 0 reg 1 1 11 reg 011 Clock Cycles 2 12 2 9 12 13 3 4 9 8 2 9 2 11 16 10 9 Comments 8 16 bit 8 16 bit 1 1 10 c I i Yti I iU I I I I 20 10 8 1 I XCHG exchlnge Register memory w...

Page 180: ...om registerlmemory 11 OOOOOs wi mod011 rim data dataifsw 01 4 16 Immediate from accumulator 10 00 1 1 1 0 wi data dataifw 1 3 4 8116 bit DEC Decrement Registerlmemory 11 111111 wi mod 00 1 rim 3 15 Re...

Page 181: ...lt Register memory and register 11 000010wl mod reg rim Immediate data and register memory 11 11 1 011 wi modOOO rim data dataifw 1 Immediate data and accumulator 11 010100wl data dataifw 1 OR Or Regl...

Page 182: ...gment offset segment selector 11 111111 1 modOl1rm mod T 11 11 1 1 0 1 0 1 disp Iow 11 1 1 a 1 00 disp Iow dlSp hlgh Reglster tmemory indirect within segment I1 11111 mod 100 rm Direct mtersegment 11...

Page 183: ...w IRET Inlerlupt return 80186 80188 CPU Table 2 9 Instruction Set Summary continued FORMAT 10 1 1 1 0 1 0 0 disp 10 1 1 1 1 1 0 0 disp 10 1 1 1 1 1 1 dlSp 10 1 1 1 0 0 1 dlSp 10 1 1 1 0 1 1 dlSp 10 1...

Page 184: ...is absent if mod 10 then OISP disp high disp Iow if rim 000 then EA BX SI OISP if rim 001 then EA BX 01 OISP if rim 010 then EA BP SI OISP if rim 011 then EA BP 01 OISP if rim 100 then EA SI OISP if r...

Page 185: ...m In iRMX 86 mode the controller operates as a slave to an external interrupt controller which operates as the master system interrupt controller Some of the interrupt control ler registers and interr...

Page 186: ...0 20 I Timer Inputs are used either as clock or pontrol signals depending upon the TMRINl 21 I programmed timer mode These inputs are active HIGH or LOW to HIGH transitions are counted and internally...

Page 187: ...D is active LOW for T T3 and Tw of any read cycle It is guaranteed not to go LOW in T until after the Address Bus is floated RD is active LOW and floats during HOLD RD is driven HIGH for one clock dur...

Page 188: ...s line is not floated during bus HOLD The address range activating LCS is software programmable MCSO 3 38 37 36 35 0 Mid Range Memory Chip Select signals are active LOW when a memory reference is made...

Page 189: ...hing and execution required for top performance will vary consid erably from one program to another a typical instruction mix on the 80186 will require greater bus usage than the 8086 This is greater...

Page 190: ...6 There are a few differences between the two processors however which must be considered These are described in the fol lowing paragraphs CPU DUTY CYCLE AND CLOCK GENERATOR The 80186 contains an inte...

Page 191: ...10 55 TCLSH Status Inactive Delay 10 65 TCLTMV Timer Output Delay 60 TCLRO Reset Delay 60 TCHQSV Queue Status Delay 35 TCHDX Status Hold Time 10 TAVCH Address Valid to Clock High 10 7 The crystal or...

Page 192: ...80186 than from the 8086 See Figure 2 7 80186 6 6 MHz Min Max Units Test Conditions 83 250 ns 10 ns 3 5 to 1 0 volts 10 ns 1 0 to 3 5 volts 33 ns 1 5 volts 33 ns 1 5 volts HOlD HlDA VERSUS RQ GT The...

Page 193: ...EI 1 FLOAT TCHCTV I lfl J f VI ___ ____ _ Y I_ __I j __ i rj J ____ I t INVALID ADDRESS _TCLCSV TCHC X TCXCSX_ Figure 2 5 Major Cycle Timing Waveforms also means that good grounds must be provided to...

Page 194: ...knowledge state 2 INTA occurs one clock later in RMX mode 3 Status inactive just prior to T4 Figure 2 5 Major Cycle Timing Waveforms continued QS1 0 0 Table 2 17 80186 Queue Status QSO Interpretation...

Page 195: ...e activated during all bus cycles whether or not the cycle addresses buffered devices The DEN signal is driven low whenever the processor is either ready to re ceive data during a read or when the pro...

Page 196: ...uired latching since the 52 signal like 50 and 51 goes to a passive state well before the beginning of T4 where RD goes inactive If 52 was directly used for this purpose the type of read command I O o...

Page 197: ...active to active transition of the WE signal In DRAM T ADO applications a DRAM controller such as the Intel 8207 or 8203 solves this problem while with iRAMs this prob lem may be solved by placing cro...

Page 198: ...write memory 1 1 1 passive signals or MULTIBU5 control signals see Figure 2 14 Use of the 8288 bus controller does not preclude the use of the 80186 generated RD WR and ALE signals however The 80186...

Page 199: ...es which control access to shared system resources refer to Intel Application Note AP 106 Multiprogram ming with the iAPX88 and iAPX86 Microsystems by George Alexy September 1980 On the 80186 the LOCK...

Page 200: ...made to only an even byte AO is driven low BHE is driven high and the data transfer occurs on 00 07 of the data bus Whenever an access is made to only an odd byte BHE is driven low AO is driven high...

Page 201: ...t with the 80186 The ad dress is latched using the address generation circuit see Figure 2 19 The AO line of each EPROM is connected to the Al address line from the 80186 NOT to the AO line Also AO si...

Page 202: ...going high to low transition of the com mand signal This action requires that both CE and WR be delayed until the address and data driven by the 80186 are guaranteed stable Figure 2 20 shows a simple...

Page 203: ...may be as narrow as 50ns if ready was returned after the first stage of the synchronizer and sub sequently changed states within the ready setup and hold time of the high to low going edge of the CPU...

Page 204: ...onous to the 80186 clock all memory requests by the 80186 must be synchronized to the 8203 before the cycle will be run To minimize this synchroni 2 38 zation time the 8203 should be used with the hig...

Page 205: ...dress refresh and directly drive 64K and 256K Dy namic RAM s in iAPX 186 and iAPX 188 systems The 8208 contains the control circuits capable of supporting one of several possible interface bus structu...

Page 206: ...r the fast or slow RAMS as programmed a_ 8208 Memory Initialization After programming is complete the 8208 performs eight RAM wake up cycles to prepare the dynamic RAM for proper device operation Duri...

Page 207: ...ut not respond to command and status inputs until programming is completed A simple means of preventing commands or status from occurring this period is to differentiate the system reset pulse to ob t...

Page 208: ...ing an upcoming bus cycle occurs during the T state immediately before the first T state of the actual bus cycle two different types of T4 and Tj can be gener ated One where the T state is immediately...

Page 209: ...e latch rather than the delay from the latch strobe which is typically longer than the propagation delay For the Intel 8282 latch this pa rameter is tIVOV the input valid to output valid delay when st...

Page 210: ...resses BHE is not present on the 8 bit 80188 All data transfers occur on the eight bits of the data bus 2 44 2_5_7 Wait State Generator The 80186 provides two ready lines a synchronous ready SRDY line...

Page 211: ...sfied by any inactive going tran sition of the ARDY line Used in this manner ARDY al lows a slow device the greatest amount of time to respond with a not ready after it has been selected In a normally...

Page 212: ...active at the beginning of either of these two cycles that cycle will be followed by a Tw Any asynchronous transition on the SRDY line not occurring at the beginning of T3 or Tw that is when the proce...

Page 213: ...time for an input transition which manages to fall within the sampling window 80186 SYNCHRONIZERS The 80186 contains synchronizers on the RES TEST TmrInO I DRQO I NMI INTO 3 ARDY and HOLD input lines...

Page 214: ...d will insert Tjstates independent of the HOLD input When the HOLD request is active the 80186 will be forced to proceed from T4 to TjsO that the bus may be relinquished See Figure 2 36 HOLD must go a...

Page 215: ...ired no idle T states will be inserted Hold not active soon enough to force idle T states 2 Greater than 25 ns tHVCL not required since it will not get recognized anyway 3 HOLD request interna ly sync...

Page 216: ...X 86 mode the integral interrupt controller op erates as a slave to an external interrupt controller which is the master system interrupt controller Vector genera tion in this mode of operation is exa...

Page 217: ...MA i e the DMA channels address the full 1 Mbyte address space of the 80186 as a flat linear array without segments When addressing I O space the upper 4 bits of the DMA pointer registers should be pr...

Page 218: ...by the CPU This means the CPU can for example modify the DMA source pointer register after 137 DMA transfers have occurred and have the new pointer value used for the 138th DMA transfer If more than...

Page 219: ...ll for unsynchronized DMA transfers The 80186 DMA controller handles two types of inter nally synchronized DMA transfers the first Timer 2 gen erates the DMA request and the second where the DMA chann...

Page 220: ...The 80186 does not generate an explicit DMA acknowl edge signal Instead a read or write directly to the DMA requesting device is performed A DMA acknowledge 2 54 signal can be generated if required b...

Page 221: ...request to clock low 25 ns min to guarantee recognition 2 Synchronizer resolution time 3 DMA unit priority arbitration etc time 4 Bus Interface Unit latches DMA request and decides to run DMA cycle 80...

Page 222: ...MA transfer When the DMA unit relinquishes the bus the CPU may resume bus operation e g instruction fetching memory or I O reads or writes etc Typically a CPU initiated bus cycle will be inserted betw...

Page 223: ...alter nate their count between two different MAX COUNT val ues programmed by the user If a single MAX COUNT register is used the timer output pin switches LOW for a single clock one clock after the m...

Page 224: ...put pin will be ignored by the timer Ifthe CONT bit in the timer control register is set the timer will reset to zero and begin another timing cycle for every low to high transition on the input pin r...

Page 225: ...er has its own control registers that set the controller mode of operation 2 59 The interrupt controller resolves priority among simulta neous requests Nesting is provided so interrupt service routine...

Page 226: ...equ OFF32h eoLregister equ OFF22h interrupLstat equ OFF30h data segment public hour minute second msec_ msec_ db hOUL db minute_ db seconcL db data ends cgroup group code dgroup group data code segme...

Page 227: ...e CPU clock rate set the control word enable counting generate interrupts on TC continuous counting set up the interrupt controller unmask interrupts highest priority interrupt sti enable processor in...

Page 228: ...his assumes that the 80186 is running at 8 MHz The code example also assumes that the peripheral control block has not been moved from its reset location FFOO FFFF in I O space timerLcontrol equ OFF5E...

Page 229: ...been moved from its reset location FFOO FFFF in I O space timerl_control equ OFF5Eh timer LmalLcnt equ OFF5Ah timer LcnLreg equ OFF58H code segment assume cs code seLcountO initializes the 80186 time...

Page 230: ...knowledge out put lines In the cascade mode of operation when two interrupts are received from the same interrupt controller one after the other the internal controller will wait until the service rou...

Page 231: ...OMA OMA and the INTI control registers Figure 2 56 shows the for mat of the INT2 and INT3 registers In cascade mode or special fully nested mode the control words in the INT2 and INT3 registers are n...

Page 232: ...R 36H 34H 32H 30H 2EH 2CH DMAI CONTROL REGISTER DMAO CONTROL REGISTER TIMER 0 CONTROL REGISTER INTERRUPT CONTROLLER STATUS REGISTER INTERRUPT REQUEST REGISTER IN SERVICE REGISTER 2AH PRIORITY MASK REG...

Page 233: ...n master mode the 80186 interrupt controller accepts external interrupt requests only In this mode the external pins associated with the interrupt con troller may serve either as direct interrupt inpu...

Page 234: ...ter nal input goes inactive the interrupt request and also the bit in the interrupt request regis ter will also go inactive low Also if the in ter rupt input is in edge triggered mode a low to high tr...

Page 235: ...e separate internally vectored inter rupt inputs When an interrupt is received on a cascaded interrupt the priority mask bits and the in service bits in the particular interrupt control register are s...

Page 236: ...rnal interrupt controller It also must be signaled when it has the highest priority pending interrupt to know when to place its interrupt vector on the bus The INT3 Slave Interrupt Output and INTI Sla...

Page 237: ...OX push AX mov AX OIOOIlIB mov OX intO control out OX AX mov AX OIOOIlOIB mov OX inLmask out OX AX pop AX pop OX ret endp ends end example 80186JnterrupLcode This routine configures the 80186 interrup...

Page 238: ...te an integer divide instruction with a segment override prefix the longest single instruction on the 80186 Other factors can affect interrupt latency An interrupt will not be accepted between the exe...

Page 239: ...les will be generated The first external indication that an interrupt has been ac knowledged will be the processor reading the interrupt vector from the interrupt vector table to low memory Since the...

Page 240: ...rupt acknowledge cycles reading the interrupt type off the lower 8 bits of the address data bus on the second interrupt acknowledge cycle see Figure 2 66 This inter rupt response is exactly the same a...

Page 241: ...into the control register for the chip se lect line Mid range memory allows both the base address and the block size of the memory area to be programmed The only limitation is that the base address mu...

Page 242: ...ing address and memory block sizes are given in Table 2 26 Any combination of bits 6 13 not shown in Table 2 26 will result in undefined 2 76 Table 2 26 UMCS Programming Values Starting Address Memory...

Page 243: ...le operation of the MCS lines will otherwise occur Each of the four chip select lines is active for one of the four equal contiguous divisions of the mid range block Therefore if the total block size...

Page 244: ...generation unit for each access to any memory or 110 areas to which the chip select circuits respond Table 2 29 shows how the ready control bits should be pro grammed to provide this In addition the...

Page 245: ...will change on the falling edge of the os cillator signal The CLKOUT pin provides the processor X x clock signal for use outside the iAPX 186 and may be used to drive other system components All timin...

Page 246: ...ather than the asynchronous ready input the half clock cycle resolution time penalty is eliminated This input must sat isfy set up and hold times to guarantee proper operation of the circuit Ready syn...

Page 247: ...Controller and Reset Upon receipt of a RESET pulse from the RES input the local bus controller will perform the following actions Drive DEN RD and WR HIGH for one clock cycle then float NOTE RD is al...

Page 248: ...Out pins going HIGH upon RESET 2 82 Interrupt Controller and Reset Upon RESET the interrupt controller will perform the following actions All SFNM bits reset to 0 implying Fully Nested Mode All PR bi...

Page 249: ...8087 Numeric Processor Extension 3...

Page 250: ......

Page 251: ...able for the iAPX 86 10 iAPX 88 10 iAPX 186 10 and iAPX 188 10 microprocessors The following para graphs present some typical applications for microproces sors using the NPX In addition a discussion o...

Page 252: ...ction opcodes must be replaced with an interrupt instruction when the emulator is used This re placement is performed by the LlNK86 program Inter rupt vectors in the hosts interrupt vector table will...

Page 253: ...oring the control word A program segment that illustrates this technique is shown in Figure 3 5 When no CPU board space has been left for the 8087 component or memory space for its software emulator a...

Page 254: ...QSO BUSY r 16 AOO f 000 010 1 OS DO 0 31 00 0 3 16 003 0 1OK H 00 ili 0 00 015 6 006 016 7 A 00 017 8 OE m I L BO AO B1 A1 A2 3 3 AI 13 A6 Ul OE T 35 aSl OSO RafGT I 36 SSi Bfiii S7 31 A17 S4 READY 3...

Page 255: ...QS1 QS11 SRDY RESETOUT CLOCKOUT ALE INTO S2 TEST S1 S2 SO S1 SO CLK RESET SO BUSY SRO INT S1 S2 82188 CLK RESET DT R I RDY DEN I QSO QSOO QS1 QS10 RQ GTO RQ GTO RO crr1 RO crr1 C ADDRESS DATA BUSt l 8...

Page 256: ...l control word value FNSTCW if 8087 is present Control 03ffh if 8087 present Jump if no 8087 is present Figure 3 5 Test for the Existence of an 8087 iSBC 337 MULTIMODULET BOARn I BOARD OPTIONAL SOLDER...

Page 257: ...hat involve the nu meric register stack These instructions include arithmetic logical transcendental constant and data transfer operations The numeric execution unit in the NPX has a 80 bit wide data...

Page 258: ...tions Not Used By the 8087 NPX 3 8 USING THE 8087 WITH CUSTOM COPROCESSORS When designing numeric processors with custom copro cessors the designer should limit the use of ESCAPE in structions to only...

Page 259: ...transferred on the high portion of the bus The 57 status information is available during T2 T3 Tw and T4 The signal is active LOW 57 is an input which the 8087 monitors during 8086 8088 controlled bus...

Page 260: ...be one dead ClK cycle after each bus exchange Pulses are active lOW QS1 I OS1 OSO QSl and QSO provide the 8087 with status to allow tracking of the CPU QSO instruction queue OS1 OSO o lOW 0 No Operati...

Page 261: ...line is available for general system use e g an I O processor in LOCAL mode A bus master can also be connected to the 8087 s RQ OTl line In this configuration the 8087 will pass the request grant hand...

Page 262: ...have two pur poses One identifies a memory operand and the other is for certain instructions to transfer a word from memory to the coprocessor 3 12 COPROCESSOR INTERFACE TO MEMORY Coprocessor design i...

Page 263: ...ization in volves either the host or coprocessor waiting for the other to finish an operation currently in progress Since the host executes the program and has program control instruc 3 13 tions like...

Page 264: ...re a CPU instruction that accesses a memory operand read or written by a previous 8087 instruction This will ensure that the 8087 has read or written the memory operand before the CPU attempts to use...

Page 265: ...aximum mode config uration iAPX 86 88 series and the iAPX 186 188 series The address time multiplexes with the data on the first 16 8 lines of the address data bus A16 through A19 are time multiplex w...

Page 266: ...ce ARDY is asyn chronous the 82188 contains a one phase synchronizer at its ARDY input Using this synchronizer the 82188 syn chronizes only the leading edge of ARDY the 82188 pre sumes the trailing ed...

Page 267: ...ocal bus between the two consecutive byte operations performed for odd aligned word operands In contrast the 8088 will never release the local bus between two bytes of a word transfer independent of i...

Page 268: ...ATUS ill RC GTf as fHf STB 7 ROlaTil os BUSY L i L 8286 AID r rv rv i7 DATA TRANSCEIVER READY 8087 T OE ClK M REseT STATUS rV RQIGT1 o 4 RQ GT L W RESET AID r IV 8089 READY DT R c ALE DEN r l h 8288 S...

Page 269: ...load store instructions for the numeric registers forces the 8087 to release the local bus after each numeric load save instruction The longest se ries of back to back transfers required by these inst...

Page 270: ...DEN 8288 STATUS IV BUS CONTROLLER eLK f J IV r V r I IADDRESS I I I I I 1 1 I 1 1 I I 1 I I ICOMMAN I I V ISYSTE L U Dsl I I I MI J Figure 3 16 iAPX 86 22 System Two assumptions are required for the c...

Page 271: ...word into NPX environment Set initial register index Save register Bump pOinter to next register All done Figure 3 17 SMALLBLOCLNPLSAVE to force all the NPX registers empty and set the WP of field in...

Page 272: ...87 INT signal disconnected 2 The 8087 is the only interrupt in the system Connect the 8087 INT signal directly to the host s INTR input see Figure 3 20 A bus driver supplies interrupt vector 1016 for...

Page 273: ...rd Delay while 8087 saves current control register value FNDISI Disable any 8087 interrupts Set IEM bit in 8087 control register The contents of cx is Irrelevant Interrupts can now be enabled Your Cod...

Page 274: ......

Page 275: ...8089 Input Output Processor 4...

Page 276: ......

Page 277: ...between an I O pe ripheral and memory and in addition transfer data be tween two 110 devices or between two areas of memory The 8089 automatically handles transfers between dissim ilar bus widths When...

Page 278: ...ntroller de codes these lines and provides signals that selectively enable one bus or the other The BIU also distinguishes between the physical and the logical widths of system and 110 buses The physi...

Page 279: ...INTR that can be activated by soft ware to issue an interrupt request to the CPU Registers Each channel has an independent set of registers see Fig ure 4 2 that are not accessible to the other channel...

Page 280: ...bit binary numbers Signed values are repre sented in standard two s complement notation with the high order bit representing the sign 0 positive 1 neg ative The processor has no way of detecting an o...

Page 281: ...The displacement is encoded in two s complement notation with the high order bit indicating the displacement sign 0 posi tive 1 negative The range for an 8 bit displacement is 128 through 127 bytes f...

Page 282: ...ble shows the coding for mat see Table 4 4 for an operand identifier explanation along with the instruction name The instruction execu tion time and its length in bytes is shown for every combi nation...

Page 283: ...8 immed8 16 3 4 ADDBI PP IX RECORDS 2CH ADDI destination source Add Word Immediate Operands Clocks Bytes Coding Example register immed16 3 4 ADDI GB OC25BH mem16 immed16 16 26 4 5 ADDI GB POINTER 5899...

Page 284: ...s Bytes Coding Example mem8 O 7 16 2 3 CLR GAl 3 DEC destination Decrement Word By 1 Operands Clocks Bytes Coding Example register 3 2 mem16 16 26 2 3 DEC PP RETRY DECB destination Decrement Byte By 1...

Page 285: ...target Jump Unconditionally Operands Clocks Bytes Coding Example label 3 3 4 JMP READ_SECTOR JNBT source bit select target Jump if Bit Not True 0 Operands Clocks Bytes Coding Example memB 0 7 label 1...

Page 286: ...ong jump if Masked Compare Equal Operands Clocks Bytes Coding Example mem8 Iabei 14 4 5 LJMCE GBJ BYTE_FOUND LJMCNE source target Long jump if Masked Compare Not Equal Operands Clocks Bytes Coding Exa...

Page 287: ...P BUF_START 20 clocks if operand is on even address 28 if on odd address LPDI destination source Load Pointer With Doubleword Immediate Operands Clocks Bytes Coding Example ptr reg immed32 12 16 6 LPD...

Page 288: ...Logical NOT Word Operands Clocks Bytes Coding Example register 3 2 NOT MC mem16 16 26 2 3 NOT GA PARM register mem16 11 15 2 3 NOT BC GA IX LINES_LEFT NOTB destination destination source Logical NOT B...

Page 289: ...no operands Set Interrupt Service Bit Operands Clocks Byles Coding Example no operands 4 2 SINTR TSL destination set value target Test and Set While Locked Operands Clocks Bytes Coding Example mem8 i...

Page 290: ...a bit location within a byte O least significant rightmost bit 7 most significant leftmost bit set value TSL Value to which destination is set if it is found O source width WID Logical width of sourc...

Page 291: ...dressing mode that the proc essor should use to construct the effective address of a memory operand Four additional address modes are available see Table 4 11 The zero bit in the first instruction ind...

Page 292: ...inter with doubleword Immediate ARITHMETIC INSTRUCTIONS ADD Add word variable Memory to register Register to memory ADDS Add byte variable Memory to register Register to memory ADDI Add word immediate...

Page 293: ...7 543210 76543210 76543210 76543210 76543210 I0 0 0 0 0 A A 0 I 1 1 0 OM M I ollse If AA OI 10 0 0 Q 0 A A 0 I 1 1 0 11M M I offset if AA OI LOGICAL AND BIT MANIPULATION INSTRUCTIONS AND AND word vari...

Page 294: ...t it AA Ql I Memory to register RRROOAAI 1 01 01 1 M M offset if AA Ol I NOTB NOT byte variable Memory Memory to register SETB Set bit to 1 IBBBOOAAO 1101MM offset if AA Ol eLR ClearbittoO Fe0 0 A A 0...

Page 295: ...ong jump it byte is 0 JNZ Jump if word not 0 Labella register label to memory LJNZ Long jump if word not 0 label to register label to memory JNZB Jump if byte not 0 lJNZB long jump If byte not 0 JMCE...

Page 296: ...nal symbol 4 4 OPERATING MODES Communication between a CPU and the 8089 lOP occurs in two distinct modes initialization and command Initial ization is typically performed when the system is powered up...

Page 297: ...byte of 16 bit signed displacement offset Optional8 bit offset used in offset addressing Table 4 9 R B P Field Encoding are six different commands that allow the CPU to start or stop programs remove...

Page 298: ...on to the port functions as a CA Ifthe lOP is memory mapped the channels look like two memory locations and any memory reference instruction to these locations causes a channel attention An lOP channe...

Page 299: ...4 23 Symbol pe Name and Function lOCK 0 Lock The lock output signal indicates to the bus controller that the bus Is needed for more than one contiguous cycle It is set via the channel control register...

Page 300: ...ess to both mem ory variables and 110 devices located anywhere in either the CPU s megabyte memory space or in the 8089 s 64k I O space Data transfer simple arithmetic logical and address manipulation...

Page 301: ...quest the bus from the lOP the CPU is only capable of granting the bus 4 25 and must wait for the lOP to release the bus Since the request grant pulse exchange must be synchro nized both the CPU and l...

Page 302: ...et of address latches is required unless MCS 85 mutliplexed address compo nents are used exclusively and depending on the bus loading demands one 8 bit bus or two 16 bit bus data transceivers would be...

Page 303: ...8089 is designated a master it requests the bus through the 8289 Arbiter When executing the initialization se quence the 8089 first fetches the SYSBUS byte from lo cation FFFF6H The W bit bit 0 of thi...

Page 304: ...ch type of command is shown in Figure 4 15 Note that if CF contains a reserved value 0IO or 100 the channel s response is unpredictable CF COMMAND FIELD 000 UPDATE PSW 7 ICF The two start program comm...

Page 305: ...I POINTER 2 o PP RESERVED 6 PARAMETER 4 1 PARAMETER BLOCK TB POINTER 1 OR CHANNEL STATE 0 1 TASK BLOCK POINTER 1 1 2 o BLOCK i POINTER 2 BUSY ICCW _C JL _ 0 PP RESERVED 6 1 PARAMETER 4 BLOCK m CF 101...

Page 306: ...ycle is determined by the source and destination logical bus widths and the address boundary odd or even ad dress DMA transfers are performed between dissimilar bus widths by assembling bytes or disas...

Page 307: ...ries wait states present in either bus cycle and bus arbitration times Generally when the other channel is idle the maximum DACK latency is five clock cycles l microsecond at 5 MHz excluding wait stat...

Page 308: ...e Destination Bus Cycles Total Bus Cycles Total Bus Cycles Total Required Clocks Required Clocks Required Clocks 8 8 2 1 fetch 1 store 8 2 1 fetch 1 store 8 2 1 fetch 1 store 8 8 16 3 2 fetch 1 store...

Page 309: ...pt of the last command the 8271 Floppy Disk Controller begins its DMA transfer on receipt of the last command parameter Since a translate DMA operation requires the use of all three pointer registers...

Page 310: ...M refresh cycle When maximum transfer rates are required the RAM re fresh cycle can be externally initiated by the 8089 By connecting the decoded DACK DMA acknowledge sig nal to the 8203 s REFRQ refre...

Page 311: ...tatus value of zero as an interrupt acknowledge bus cycle the bus controller s INTA output must be OR ed with its 10RC output to permit fetching of task block instructions from local 8089 memory remot...

Page 312: ...cle This allows the 8089 to enter state T4 Periods of inactivity or idle states TI can occur between bus cycles These idle states result from the execution of a long instruction or the loss of the bus...

Page 313: ...Table 4 19 Bus Cycle Decoding Status Output Bus Cycle Indicated Bus Controller S2 S1 SO Command Output 0 0 0 Instruction fetch from 1 0 space INTA 0 0 1 Data read from 110 space 10RC 0 1 0 Data write...

Page 314: ...e use of a private 110 bus between two lOP s In this instance one lOP is designated the master and the other is designated the slave However the only difference between a master and a slave running in...

Page 315: ...Both must be initialized to use the same request grant mode Normally mode 1 will be selected for its improved responsiveness and the des ignation of master will be arbitrary If one lOP must have the I...

Page 316: ...ycles The following line of code will repeatedly test a semaphore pointed to by GA until it is found to contain zero TEST_FLAG TSL GA OFFH TEST_FLAG When the semaphore is found to be zero it is set to...

Page 317: ...80130 Operating System Firmware 5...

Page 318: ......

Page 319: ...ble 5 3 In addition Table 5 4 lists the mnemonic codes for both unavoidable and avoidable exceptions along with the numeric values assigned to each mnemonic exceptor If your compiler supports the SELE...

Page 320: ...AMMABLE INTERRUPT CONTROLLER PIC PIC Commands The PIC accepts two types of command words from the CPU a Initialization Command Words ICW s Before normiu operation can begin the PIC must be ini tialize...

Page 321: ...h the exception of ICW3 ICW5 and ICW6 if not specified in ICWI The PIC is ready to accept interrupts after the last ICW is sent Bits 7 6 00 Unused but set to 0 Bit 5 0 All inputs are non local URI 1 a...

Page 322: ...Instruction Fetch 1 0 1 MEMRD 1 1 X Passive ClK I The system clock provides the basic timing for the processor and bus controller The 80130 uses the system clock as an input to the SYSTICK and BAUD ti...

Page 323: ...Initialization Command Word 6 ICW6 ICW6 is sent if specified in ICWI and selects IR inputs as being either local of non local During an interrupt ac knowledge cycle the URI output is driven to zero in...

Page 324: ...PARAM DELETE MAILBOX Deletes a mailbox E OK E EXIST E TYPE DELETE REGION Deletes a region E OK E CONTEXT E EXIST E TYPE DELETE SEGMENT Deletes a segment E OK E EXIST E TYPE DELETE TASK Deletes a task...

Page 325: ...rned E EXIST E TIME E TYPE RESET INTERRUPT Cancels the assignment of an interrupt handler to an E OK interrupt line E CONTEXT E PARAM RESUME TASK Decreases by one the suspension depth of a task E OK E...

Page 326: ...Register 1 Read In service Register Reading the Interrupt Mask Register IMR The IMR is an 8 bit register that indicates which IR inputs are masked interrupts are inhibited IMR is read by reading from...

Page 327: ...vel has reached its user specified saturation point for interrupt service requests No further interrupts will be allowed on the level until the interrupt task executes a WAIT INTERRUPT This error is o...

Page 328: ...ng the appropriate control word followed by the least signifi cant byte of the count value and then the most significant byte The 80130 timers are connected to the lower half of the data bus and are a...

Page 329: ...must be sent prior to sending the two bytes of the count value The initialization words and the meaning of the encoding is as follows Timer o 1 Initialization Word 00110100B 01110000B 5 11 2 Bits 7 6...

Page 330: ...igh level as an interrupt request If the IR input remains active after the EXIT INTERRUPT primi tive has been executed another interrupt request is gener ated This will be recognized only if the proce...

Page 331: ...80130 component sets the highest prior ity interrupt and resets the corresponding edge detect 5 13 latch The 80130 does not drive the addressldata bus during this bus cycle but does acknowledge the c...

Page 332: ...al must be active early in a memory or I O cycle to allow activation of ACK early enough to prevent wait states There are two schemes for implementc ing ready signals normally ready and normally not r...

Page 333: ...In this case the effective address of the I O block which must be specified during the system configuration step could be OOOOH or any other multiple of 16 be tween OOOOH and 7FFOH 5 15 The OSP will...

Page 334: ......

Page 335: ...Index...

Page 336: ......

Page 337: ...0186 Extemal Chip Select Device 2 35 8086 80186 8087 OPERATION 3 12 8086 and Coprocessor On the Local Bus 1 129 8086 Bus 2 24 8086 Bus Timing Maximum Mode System 1 103 8086 Bus Timing Minimum Mode Sys...

Page 338: ...1 23 1 38 1 130 2 24 2 31 8288 Bus Controller Block Diagram 1 131 8288 Outputs During Passive Modes 1 119 8289 Bus Arbiter 1 98 1 133 4 38 8289 Bus Arbiter Block Diagram 1 133 8289 Multi master Bus A...

Page 339: ...tput INS OUTS Instructions 2 5 Block Transfer Mode 1 144 Block Transfer to 16 bit lIO Using 1 92 Block Transfer to 8 bit I O Using 1 92 Boolean Operators and 1 14 inclusive Or 1 14 not 1 14 Boundaries...

Page 340: ...edge 1 65 Read 1 64 1 65 Write 1 64 1 65 COMMON CONTROL UNIT CCU 4 1 Common IAPX186 System Components 2 4 Common Word Address 2 33 INDEX Communication Chips 1 2 COMPATIBILITY WITH FRSTOR 3 19 COMPATIB...

Page 341: ...Transfers 2 56 Destination Synchronized Transfer Cycle 4 32 Device Architecture 801861188 2 1 Device Assignment 1 91 Device Output Drivers 1 92 DEVICE PIN ASSIGNMENTS 3 8 4 20 5 1 DEVICE PIN DEFINITIO...

Page 342: ...UNIT 2 1 External Bus 16 bit 80186 2 1 8 bit 80188 2 1 External Clock Generator 2 24 External DMA Controller 2 35 EXTERNAL FREQUENCY CLOCK REFERENCE 1 126 2 80 External Frequency For Multiple 8284 s 1...

Page 343: ...20 Bus Operation 3 15 Idle Cycle 1 142 Idle Cycles Tl 1 66 Idle Status 1 115 Idle T States Ti 2 19 IF Flag 1 122 Immediate Operand 8 bit Port Number 1 21 Immediate Operands Limitations 1 18 Implicit...

Page 344: ...t 2 23 String 1 15 2 9 String Manipulation 2 7 String Move 2 4 2 5 Target 1 23 TEST 1 14 2 8 Timing Cycles 1 12 2 12 Unconditional 1 16 Unconditional Transfer 1 16 2 10 WAIT 1 64 1 105 1 122 2 33 INTO...

Page 345: ...g Timing Requirements 1 141 IRMX 86 Interrupt Controller Interconnection 2 66 IRMX 86 Mode 2 19 IRMX 86 MODE OPERATION 2 64 IRMX Mode 2 70 INDEX IRMX Mode Sources 2 68 ISBC 337 MULTIMODULE 3 3 ISBC 33...

Page 346: ...e 1 18 Memory Organization 2 4 Memory Read 1 4 Memory Read Signals 1 105 Memory Reference Escape Instruction Form 3 8 Memory Reference Opcodes 3 7 Memory Space 2 3 8086 1 5 8086 8088 1 8 8088 1 5 INDE...

Page 347: ...ion 3 2 Numeric Instruction Opcodes 3 2 NUMERIC PROCESSOR EXTENSION APPLICATIONS 3 1 Numerically Based Applications 3 1 o Odd Address Boundary 1 117 Odd Memory Address 1 23 Offset Memory Variable 1 9...

Page 348: ...1 7 Disk resident 1 10 Dynamically Relocatable 1 10 Inactive 1 10 Position independent 1 10 Programmable 16 bit Timer counters 2 3 PROGRAMMABLE DIRECT MEMORY ACCESS UNIT 2 3 Two Channel 2 1 Programma...

Page 349: ...ommand 1 148 Communications 1 3 2 1 Count CX 1 16 CS 1 5 1 120 1 123 1 124 2 9 Current Address 1 45 Current Code Segment 1 124 CX 1 17 1 68 2 5 2 9 Data 1 7 INDEX 01 1 15 2 5 DS I 5 DX 1 21 1 85 1 91...

Page 350: ...e processor Systems 1 1 Single step Flags 1 124 Single step Mode 1 7 Sixteen Bit I O 1 88 Small8088 Based System 1 2 SMALL LOCK NP ESTORE 3 21 SMALL LOCK NPX SAVE 3 21 software Based 8087 Emulator 3 1...

Page 351: ...ssor System Bus Signal Connections 3 16 Time multiplexed 1 1 TIMER APPLICATIONS 2 58 Timer Block Diagram 2 57 Timer Control Block Format 2 57 TIMER INPUT PIN OPERATION 2 57 TIMER OUTPUT PIN OPERATION...

Page 352: ...es TW 1 66 Word Memory Location 2 6 INDEX Word Memory Read 1 109 Word Memory 16 bit 1 78 Word Operations 2 5 Word Transfer 1 112 Worst Case Local Bus Request Wait Times In Clocks 3 28WR 3 26WR Status...

Page 353: ......