Hardware Design Guide
53
IXP28XX Network Processor
QDR SRAM
QDR SRAM
4
The Intel
®
IXP2800 and Intel
®
IXP2850 Network Processors have four independent SRAM
controllers, each of which supports pipelined QDR synchronous static RAM (SRAM) and/or a
coprocessor that adheres to QDR signaling. Any or all controllers can be left unpopulated if the
application does not need to use them. SRAM is accessible by the Microengines, the Intel XScale
®
core, and the PCI Unit (external bus masters and DMA).
The memory is logically four bytes (32 bits) wide; physically, the data pins are two bytes wide and
are double-clocked. Byte parity is supported, and each of the four bytes has a parity bit, which is
written when the byte is written and checked when the data is read. There are byte-enables that
select the bytes to be written, for writes of less than 32 bits.
Each of the four QDR ports are QDR- and QDRII-compatible, and each port implements the “_K”
and “_C” output clocks and the “_CIN” clock (and their inversions) as inputs.
Note:
The “_C” and “_CIN” clocks are optional. Extensive work has been done to provide impedance
controls within the IXP28XX network processors for the signals initiated by the network processor
driving to QDR parts. A clean signaling environment is critical to achieving 200- to 233-MHz
QDRII data transfers.
The configuration assumptions for the network processor I/O driver and/or receiver development
include four QDR loads and the network processor. The network processor supports bursts of two
SRAMs; four-SRAM bursts are not supported.
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR electricals and protocol. Each SRAM controller can also interface to an external
coprocessor through its standard QDR interface, which enables SRAM devices and coprocessors to
operate on the same bus. The coprocessor behaves as a memory-mapped device on the SRAM bus.
4.1
Introduction
This is a design guide for the QDR interface of IXP28XX NPU. It is intended to guide board
designers using IXP28XX network processor in their designs employing 4 SRAM loads or less at a
clock frequency of 233/250MHz. If a much lower frequency is to be used then it is recommended
that the developer consult with the SRAM vendor to ensure that the SRAM operates at that
intended frequency.
These guidelines are based on a set of simulations that were performed under optimum or close to
optimum conditions. The QDR section of the base board of IXDP2400 platform has been used to
simulate all IXP28XX QDR signals. The routing guidelines in this guide are modified from those
employed in IXDP2400 platform. It is very important that these guidelines be observed and
adhered to as closely as possible to obtain working designs.
However,
if the customer is interested in using a different design scheme then we strongly
recommend the customer to do full extended simulations on the intended design scheme
.Any
changes or modifications to the design guidelines described here in this document may lead to
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