Hardware Design Guide
55
IXP28XX Network Processor
QDR SRAM
Each channel can be expanded by depth, according to the number of port-enables available. If
external decoding is used, then the number of SRAMs used is not limited by the number of port
enables generated by the SRAM controller.
Note:
External decoding may require external pipeline registers to account for the decode time,
depending on the desired frequency.
Table 15
lists the QDR Address and Read Port Enable (RPE)/Write Port Enable (WPE) mapping.
Table 16
shows maximum SRAM system sizes. Shaded entries require external decoding, because
they use more port-enables than the SRAM controller can supply directly.
Table 14.
SRAM Controller Configurations
SRAM
Configuration
SRAM Size
Addresses Needed
to Index SRAM
Addresses Used
as Port-enables
Total Number of
Port-select Pairs
Available
512K x 18
1 Mbyte
17:0
23:22, 21:20
4
1M x 18
2 Mbytes
18:0
23:22, 21:20
4
2M x 18
4 Mbytes
19:0
23:22, 21:20
4
4M x 18
8 Mbytes
20:0
23:22
3
8M x 18
16 Mbytes
21:0
23:22
3
16M x 18
32 Mbytes
22:0
None
2
32M x 18
64 Mbytes
23:0
None
1
Table 15.
QDR Address/RPE/WPE Mapping
SRAM
Configuration/Size
SRAM_CONTROL
[SRAM_SIZE][9:7]
SRAM_CONTROL
[PORT_CTL][5:4]
RPE[2]/WPE[2]
RPE[3]/WPE[3]
512K x 18 - 1 Mbyte
000
11
QDR_ADDR[23:22]
QDR_ADDR[21:20]
1Mb x 18 - 2 Mbytes
001
11
QDR_ADDR[23:22]
QDR_ADDR[21:20]
2Mb x 18 - 4 Mbytes
010
11
QDR_ADDR[23:22]
QDR_ADDR[21:20]
4Mb x 18 - 8 Mbytes
011
10
QDR_ADDR[23:22]
N/A
8Mb x 18 - 16 Mbytes
100
10
QDR_ADDR[23:22]
N/A
16Mb x 18 - 32 Mbytes
101
00
N/A
N/A
32Mb x 18 - 64 Mbytes
110
00
N/A
N/A
Table 16.
Total Memory per Channel (Sheet 1 of 2)
SRAM Size
Number of SRAMs on Channel
1
2
3
4
5
6
7
8
512K x 18
1 Mbyte
2 Mbytes
3 Mbytes
4 Mbytes
5 Mbytes
6 Mbytes
7 Mbytes
8 Mbytes
1M x 18
2 Mbytes
4 Mbytes
6 Mbytes
8 Mbytes
10 Mbytes
12 Mbytes
14 Mbytes
16 Mbytes
2M x 18
4 Mbytes
8 Mbytes
12 Mbytes
16 Mbytes
20 Mbytes
24 Mbytes
28 Mbytes
32 Mbytes
4M x 18
8 Mbytes
16 Mbytes
24 Mbytes
32 Mbytes
64 Mbytes
NA
NA
NA
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