1-2
COMPONENT INTRODUCTION
family systems which are integrated into this single component. This integration results in the
Pentium Pro processor bus more closely resembling a symmetric multi-processing (SMP) sys-
tem bus rather than a previous generation processor-to-cache bus. This added level of integration
and improved performance results in higher power consumption and a new bus technology. This
means it is more important than ever to ensure adherence to the specifications contained in this
document.
1.1.
BUS FEATURES
The design of the external Pentium Pro processor bus enables it to be “multiprocessor ready.”
Bus arbitration and control, cache coherency circuitry, an MP interrupt controller and other sys-
tem-level functions are integrated into the bus interface.
To relax timing constraints, the Pentium Pro processor implements a synchronous, latched bus
protocol to enable a full clock cycle for signal transmission and a full clock cycle for signal in-
terpretation and generation. This latched protocol simplifies interconnect timing requirements
and supports higher frequency system designs using inexpensive ASIC interconnect technology.
The Pentium Pro processor bus uses low-voltage-swing GTL+ I/O buffers, making
high-frequency signal communication easier.
All output pins are actually implemented in the Pentium Pro processor as I/O buffers. This buffer
design complies with IEEE 1149.1 Boundary Scan Specification, allowing all pins to be sam-
pled and tested. An output only buffer is used only for TDO, which is not sampled in the bound-
ary scan chain. A pin is an output pin when it is not an input for normal operation or FRC.
Most of the Pentium Pro processor cache protocol complexity is handled by the processor. A
non-caching I/O bridge on the Pentium Pro processor bus does not need to recognize the cache
protocol and does not need snoop logic. The I/O bridge can issue standard memory accesses on
the Pentium Pro processor bus, which are transparently snooped by all Pentium Pro processor
bus agents. If data is modified in a Pentium Pro processor cache, the processor transparently pro-
vides data on the bus, instead of the memory controller. This functionality eliminates the need
for a back-off capability that existing I/O bridges require to enable cache writeback cycles. The
memory controller must observe snoop response signals driven by the Pentium Pro processor
bus agents, absorb writeback data on a modified hit, and merge any write data.
The Pentium Pro processor integrates memory type range registers (MTRRs) to replace the ex-
ternal address decode logic used to decode cacheability attributes.
The Pentium Pro processor bus protocol enables a near linear increase in system performance
with an increase in the number of processors. The Pentium Pro processor interfaces to a multi-
processor system without any support logic. This “glueless” interface enables a desktop system
to be built with an upgrade socket for another Pentium Pro processor.
The external Pentium Pro processor bus and Pentium Pro processor use a ratio clock design that
provides modularity and an upgrade path. The processor internal clock frequency is an n/2 mul-
tiple of the bus clock frequency where n is an integer equal to or greater than 4 but only certain
bus and processor frequency combinations are supported. Additional combinations are reserved
by this specification to provide future upgrade paths. See Section 9.2., “Clock Frequencies and
Ratios” for the bus and processor frequencies and combinations.
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......